x86/rocketlake/pipeline.json

7 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
117         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
135 …"BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX …
139 …"PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RE…
166 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
190 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
324 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
337         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
340 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
345         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
349 …"PublicDescription": "Counts the number of instructions retired - an Architectural PerfMon event. …
379 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
383 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
417 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
449 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
458 …"PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream…
467 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
475 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
490         "BriefDescription": "Self-modifying code (SMC) detected.",
493 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
517 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
532 … This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch misp…
543 …servation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (s…
548 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
551 …-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued…
559 …t were issued but not retired from the speculative path as well as the out-of-order engine recover…
564 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
566 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
571 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
574 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
590 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
598 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
606 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
614 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
622 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
630 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
638 …"PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dis…
651 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
655 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
660 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
664 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
669 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
673 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
678 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
682 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
687         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
691         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
696         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
700         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
705         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
709         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
714         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
718         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
733         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
766 …"BriefDescription": "Uops inserted at issue-stage in order to preserve upper bits of vector regist…
769 …tel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destinatio…