x86/meteorlake/cache.json

384         "BriefDescription": "Retired load instructions.",
389 …"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch in…
395         "BriefDescription": "Retired store instructions.",
400         "PublicDescription": "Counts all retired store instructions.",
406         "BriefDescription": "All retired memory instructions.",
411         "PublicDescription": "Counts all retired memory instructions - loads and stores.",
417         "BriefDescription": "Retired load instructions with locked access.",
422         "PublicDescription": "Counts retired load instructions with locked access.",
428         "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
433 …   "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
439         "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
444 …  "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
450         "BriefDescription": "Retired load instructions that hit the STLB.",
455 …"PublicDescription": "Number of retired load instructions with a clean hit in the 2nd-level TLB (S…
461         "BriefDescription": "Retired store instructions that hit the STLB.",
466 … "PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB).",
472         "BriefDescription": "Retired load instructions that miss the STLB.",
477 …"PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB…
483         "BriefDescription": "Retired store instructions that miss the STLB.",
488 …"PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TL…
503 …"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared …
508 …"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from…
514 …"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hit…
519 …"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core s…
525 …"BriefDescription": "Retired load instructions whose data sources were HitM responses from shared …
530 …"PublicDescription": "Counts retired load instructions whose data sources were HitM responses from…
536 …"BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop…
541 …"PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cros…
547 …"BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops r…
552 …"PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without …
558 …"BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hit…
563 …"PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core s…
569 …"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from loca…
574 …"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from loc…
580         "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
585 …"PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or a…
596 …"PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1…
602         "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
607 …"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 da…
613         "BriefDescription": "Retired load instructions missed L1 cache as data sources",
618 …"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1…
624         "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
629         "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
635         "BriefDescription": "Retired load instructions missed L2 cache as data sources",
640         "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
646         "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
651 …"PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 ca…
657         "BriefDescription": "Retired load instructions missed L3 cache as data sources",
662 …"PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3…
668 …"BriefDescription": "Counts the number of load ops retired that miss the L3 cache and hit in DRAM",
677         "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache.",
686         "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache.",
695         "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache.",
704         "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache.",
713         "BriefDescription": "Counts the number of load ops retired that hit in the L3 cache.",
771         "BriefDescription": "Counts the number of load ops retired.",
781         "BriefDescription": "Counts the number of store ops retired.",
791 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
803 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
815 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
827 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
839 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
851 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
863 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
875 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
887 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
899 …"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency thresho…
911 …     "BriefDescription": "Counts the number of load uops retired that performed one or more locks",
921         "BriefDescription": "Counts the number of memory uops retired that were splits.",
931         "BriefDescription": "Counts the number of retired split load uops.",
941         "BriefDescription": "Counts the number of retired split store uops.",
951 …"BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES…
961         "BriefDescription": "Retired memory uops for any access",
964 …"PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",