x86/ivybridge/ivb-metrics.json

3         "BriefDescription": "C2 residency percent per package",
4         "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
10         "BriefDescription": "C3 residency percent per core",
11         "MetricExpr": "cstate_core@c3\\-residency@ / TSC",
17         "BriefDescription": "C3 residency percent per package",
18         "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
24         "BriefDescription": "C6 residency percent per core",
25         "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
31         "BriefDescription": "C6 residency percent per package",
32         "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
38         "BriefDescription": "C7 residency percent per core",
39         "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
45         "BriefDescription": "C7 residency percent per package",
46         "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59         "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
78 …sible; which incur a few cycles load re-issue. However; the short re-issue duration is often hidde…
96 …er-cases for operations that cannot be handled natively by the execution pipeline. For example; wh…
102         "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma_retiring)",
107 …-of-order scheduler dispatches ready uops into their respective execution units; and once complete…
112 …"MetricExpr": "(UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (INT_MISC.RECOVERY_CYCLES_ANY / …
117 …s for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For…
128 …etched from an incorrectly speculated program path; or stalls when the out-of-order part of the ma…
137 … corrected path; following all sorts of miss-predicted branches. For example; branchy code with lo…
143         "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
147 … as in the case of read-modify-write as an example. Since these instructions require multiple uops…
161 …"BriefDescription": "This metric represents fraction of slots where Core non-memory issues were of…
163         "MetricExpr": "tma_backend_bound - tma_memory_bound",
168 …-memory issues were of a bottleneck.  Shortage in hardware compute resources; or dependencies in s…
172 …n of cycles while the memory subsystem was handling synchronizations due to data-sharing accesses",
178 … cycles while the memory subsystem was handling synchronizations due to data-sharing accesses. Dat…
193 …"MetricExpr": "(1 - MEM_LOAD_UOPS_RETIRED.LLC_HIT / (MEM_LOAD_UOPS_RETIRED.LLC_HIT + 7 * MEM_LOAD_…
202 …"MetricExpr": "(IDQ.ALL_DSB_CYCLES_ANY_UOPS - IDQ.ALL_DSB_CYCLES_4_UOPS) / tma_info_core_core_clks…
215 …o switches from DSB to MITE pipelines. The DSB (decoded i-cache) is a Uop Cache where the front-en…
224 …-aside Buffers) are processor caches for recently used entries out of the Page Tables that are use…
228 …: "This metric roughly estimates the fraction of cycles spent handling first-level data TLB store …
233 …-level data TLB store misses.  As with ordinary data caching; focus on improving data locality and…
242 …hreading hiccup; where multiple Logical Processors contend on different data-elements mapped into …
257         "MetricExpr": "tma_frontend_bound - tma_fetch_latency",
267 …"MetricExpr": "4 * min(CPU_CLK_UNHALTED.THREAD, IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE) /…
272 …he CPU was stalled due to Frontend latency issues.  For example; instruction-cache misses; iTLB mi…
276 …"BriefDescription": "This metric represents overall arithmetic floating-point (FP) operations frac…
281 …-point (FP) operations fraction the CPU has executed (retired). Note this metric's value may excee…
285 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction …
290 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) scalar uops fraction…
294 …"BriefDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction …
299 …"PublicDescription": "This metric approximates arithmetic floating-point (FP) vector uops fraction…
309 …-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into mi…
313 … slots where the CPU was retiring heavy-weight operations -- instructions that require two or more…
319 …he CPU was retiring heavy-weight operations -- instructions that require two or more uops or micro…
324         "MetricExpr": "ICACHE.IFETCH_STALL / tma_info_thread_clks - tma_itlb_misses",
338 …"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lo…
351         "BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
363 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
440         "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
446         "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
452         "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
476 …"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core…
483 …"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is…
488 …ublicDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is …
509 …      "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
515         "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
521         "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
527         "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
540 …"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is …
575 … supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
612 …"MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / (CPU_CLK_UNHALTED.REF_XCLK_ANY / 2) if #S…
629 …   "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
641         "BriefDescription": "The ratio of Executed- by Issued-Uops",
645 …"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop m…
654 …"BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor…
684 …"MetricExpr": "max((min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) - CYCLE_ACTIVI…
688 … TLB. These cases are characterized by execution unit stalls; while some non-completed demand load…
693 …"MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY.STALLS_L2_PENDING) / tma_info_t…
730 …slots where the CPU was retiring light-weight operations -- instructions that require no more than…
731         "MetricExpr": "tma_retiring - tma_heavy_operations",
736 …-weight operations -- instructions that require no more than one uop (micro-operation). This corre…
742 …"MetricExpr": "(UOPS_DISPATCHED_PORT.PORT_2 + UOPS_DISPATCHED_PORT.PORT_3 - UOPS_DISPATCHED_PORT.P…
752 …"MetricExpr": "MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES * min(CPU_CLK_UNHALTED.TH…
762         "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts",
767 …-of-order portion of the machine needs to recover its state after the clear. For example; this can…
772 …"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\…
776 …-core traffic is generated by all IA cores. This metric does not aggregate non-data-read requests …
781 …"MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD) / tm…
791 …min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.STALLS_LDM_PENDING) + RESOURCE_STALLS.SB) / (min(CPU_C…
796 …o demand load or store instructions. This accounts mainly for (1) non-completed in-flight memory d…
810 …"MetricExpr": "(IDQ.ALL_MITE_CYCLES_ANY_UOPS - IDQ.ALL_MITE_CYCLES_4_UOPS) / tma_info_core_core_cl…
814 …the legacy decode pipeline). This pipeline is used for code that was not pre-cached in the DSB or …
823 … Commonly used instructions are optimized for delivery by the DSB (decoded i-cache) or MITE (legac…
845 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
850 …ion of cycles CPU dispatched uops on execution port 2 ([SNB+]Loads and Store-address; [ICL+] Loads…
854 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
859 …ion of cycles CPU dispatched uops on execution port 3 ([SNB+]Loads and Store-address; [ICL+] Loads…
863 …is metric represents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data)",
868 …sents Core fraction of cycles CPU dispatched uops on execution port 4 (Store-data). Sample with: U…
881 … the CPU performance was potentially limited due to Core computation issues (non divider-related)",
883 …min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_EXECUTE) + UOPS_EXECUTED.CYCLES_GE_1_UOP_EXE…
887 …-related).  Two distinct categories can be attributed into this metric: (1) heavy data-dependency …
892 …ORE\\,inv\\,cmask\\=1@ / 2 if #SMT_on else (min(CPU_CLK_UNHALTED.THREAD, CYCLE_ACTIVITY.CYCLES_NO_…
896 …t (Logical Processor cycles since ICL, Physical Core cycles otherwise). Long-latency instructions …
901 …_EXECUTED.CORE\\,cmask\\=1@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=2@) / 2 if #SMT_on else (UOPS_EXECU…
905 …-dependency among software instructions; or over oversubscribing a particular hardware resource. I…
910 …_EXECUTED.CORE\\,cmask\\=2@ - cpu@UOPS_EXECUTED.CORE\\,cmask\\=3@) / 2 if #SMT_on else (UOPS_EXECU…
914 …cal Core cycles otherwise).  Loop Vectorization -most compilers feature auto-Vectorization options…
932 …ions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is …
936 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
942 … estimates fraction of cycles handling memory load split accesses - load that cross 64-byte cache …
951 …resents rate of split store accesses.  Consider aligning your data to the 64-byte cache line granu…
955 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
960 …f cycles where the Super Queue (SQ) was full taking into account all request-types and both hardwa…
964 … CPU was stalled  due to RFO store memory accesses; RFO store issue a read-for-ownership request b…
969 …ses; RFO store issue a read-for-ownership request before the write. Even though store accesses do …
978 …perations in the pipeline; a load can avoid waiting for memory if a prior in-flight store is writi…
984 … * 9 * (1 - MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOC…
988 …-of-order core performance; however; holding resources for longer time can lead into undesired imp…