x86/haswell/cache.json

51         "BriefDescription": "Not rejected writebacks that hit L2 cache",
54         "PublicDescription": "Not rejected writebacks that hit L2 cache.",
59         "BriefDescription": "L2 cache lines filling L2",
62 …event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2…
67         "BriefDescription": "L2 cache lines in E state filling L2",
70         "PublicDescription": "L2 cache lines in E state filling L2.",
75         "BriefDescription": "L2 cache lines in I state filling L2",
78         "PublicDescription": "L2 cache lines in I state filling L2.",
83         "BriefDescription": "L2 cache lines in S state filling L2",
86         "PublicDescription": "L2 cache lines in S state filling L2.",
91         "BriefDescription": "Clean L2 cache lines evicted by demand",
94         "PublicDescription": "Clean L2 cache lines evicted by demand.",
99         "BriefDescription": "Dirty L2 cache lines evicted by demand",
102         "PublicDescription": "Dirty L2 cache lines evicted by demand.",
107         "BriefDescription": "L2 code requests",
110         "PublicDescription": "Counts all L2 code requests.",
119         "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
124         "BriefDescription": "Demand requests that miss L2 cache",
128         "PublicDescription": "Demand requests that miss L2 cache.",
133         "BriefDescription": "Demand requests to L2 cache",
137         "PublicDescription": "Demand requests to L2 cache.",
142         "BriefDescription": "Requests from L2 hardware prefetchers",
145         "PublicDescription": "Counts all L2 HW prefetcher requests.",
150         "BriefDescription": "RFO requests to L2 cache",
153         "PublicDescription": "Counts all L2 store RFO requests.",
158         "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
161         "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
166         "BriefDescription": "L2 cache misses when fetching instructions",
169         "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
174         "BriefDescription": "Demand Data Read requests that hit L2 cache",
178 …Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache",
183         "BriefDescription": "Demand Data Read miss L2, no rejects",
187         "PublicDescription": "Demand data read requests that missed L2, no rejects.",
192         "BriefDescription": "L2 prefetch requests that hit L2 cache",
195         "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
200         "BriefDescription": "L2 prefetch requests that miss L2 cache",
203         "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
208         "BriefDescription": "All requests that miss L2 cache",
212         "PublicDescription": "All requests that missed L2.",
217         "BriefDescription": "All L2 requests",
221         "PublicDescription": "All requests to L2 cache.",
226         "BriefDescription": "RFO requests that hit L2 cache",
229         "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
234         "BriefDescription": "RFO requests that miss L2 cache",
237         "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
242         "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
245         "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
250         "BriefDescription": "Transactions accessing L2 pipe",
253         "PublicDescription": "Transactions accessing L2 pipe.",
258         "BriefDescription": "L2 cache accesses when fetching instructions",
261         "PublicDescription": "L2 cache accesses when fetching instructions.",
266         "BriefDescription": "Demand Data Read requests that access L2 cache",
269         "PublicDescription": "Demand data read requests that access L2 cache.",
274         "BriefDescription": "L1D writebacks that access L2 cache",
277         "PublicDescription": "L1D writebacks that access L2 cache.",
282         "BriefDescription": "L2 fill requests that access L2 cache",
285         "PublicDescription": "L2 fill requests that access L2 cache.",
290         "BriefDescription": "L2 writebacks that access L2 cache",
293         "PublicDescription": "L2 writebacks that access L2 cache.",
298         "BriefDescription": "RFO requests that access L2 cache",
301         "PublicDescription": "RFO requests that access L2 cache.",
412         "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
422         "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
428         "PublicDescription": "Retired load uops missed L2. Unknown data source excluded.",
781         "BriefDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
790         "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",