x86/goldmontplus/cache.json

18         "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.",
29 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac…
59 …"BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise ev…
159         "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
169         "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
179         "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
216 …nd & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
221 …nd & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
226 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
231 …tch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
236 …"BriefDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time o…
241 …"PublicDescription": "Counts data reads (demand & prefetch) outstanding, per cycle, from the time …
266 …L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
271 …L2 prefetchers miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
276 … L1 or L2 prefetchers true miss for the L2 cache with a snoop miss in the other processor module.",
281 …hers true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
286 …"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, f…
291 …"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers outstanding, per cycle, …
316 …nd & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
321 …nd & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
326 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
331 …tch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
336 …ad, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
341 …ad, and read for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
366 …core subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
371 …core subsystem miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
376 … the uncore subsystem true miss for the L2 cache with a snoop miss in the other processor module.",
381 …stem true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
386 …"BriefDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the time…
391 …"PublicDescription": "Counts requests to the uncore subsystem outstanding, per cycle, from the tim…
416 …nd & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
421 …nd & prefetch) miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
426 …s (demand & prefetch) true miss for the L2 cache with a snoop miss in the other processor module.",
431 …tch) true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
436 …Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
441 …Counts reads for ownership (RFO) requests (demand & prefetch) outstanding, per cycle, from the tim…
466 … lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
471 … lock requests miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
476 …d split lock requests true miss for the L2 cache with a snoop miss in the other processor module.",
481 …ests true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
486 …"BriefDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the time…
491 …"PublicDescription": "Counts bus lock and split lock requests outstanding, per cycle, from the tim…
516 …ache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
521 …ache evictions miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
526 …or L2 cache evictions true miss for the L2 cache with a snoop miss in the other processor module.",
531 …ions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
536 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
541 … of writeback transactions caused by L1 or L2 cache evictions outstanding, per cycle, from the tim…
546 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
551 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
556 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th…
561 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t…
566 … cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a s…
571 … cacheline and I-side prefetch requests that miss the instruction cache miss the L2 cache with a s…
576 …eline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with…
581 …eline and I-side prefetch requests that miss the instruction cache true miss for the L2 cache with…
586 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache ou…
591 …ounts demand instruction cacheline and I-side prefetch requests that miss the instruction cache ou…
616 …ll cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
621 …ll cache lines miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
626 …s of full cache lines true miss for the L2 cache with a snoop miss in the other processor module.",
631 …ines true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
636 …ion": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the tim…
641 …ion": "Counts demand cacheable data reads of full cache lines outstanding, per cycle, from the tim…
666 …ata cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
671 …ata cache line miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
676 … full data cache line true miss for the L2 cache with a snoop miss in the other processor module.",
681 …line true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
686 …p (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the tim…
691 …p (RFO) requests generated by a write to full data cache line outstanding, per cycle, from the tim…
696 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
701 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
706 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
711 …ites to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes h…
716 …C) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the…
721 …C) memory region and full cache-line non-temporal writes miss the L2 cache with a snoop hit in the…
726 …mory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss i…
731 …mory region and full cache-line non-temporal writes true miss for the L2 cache with a snoop miss i…
736 …ble write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per …
741 …ble write combining (USWC) memory region and full cache-line non-temporal writes outstanding, per …
766 …che prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
771 …che prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
776 …data cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
781 …cher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
786 …che line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the tim…
791 …che line reads generated by hardware L1 data cache prefetcher outstanding, per cycle, from the tim…
816 …che prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
821 …che prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
826 …e L2 cache prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
831 …cher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
836 …ata cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the tim…
841 …ata cacheline reads generated by hardware L2 cache prefetcher outstanding, per cycle, from the tim…
866 … L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
871 … L2 prefetcher miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
876 …ated by L2 prefetcher true miss for the L2 cache with a snoop miss in the other processor module.",
881 …cher true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
886 …reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the tim…
891 …reads for ownership (RFO) requests generated by L2 prefetcher outstanding, per cycle, from the tim…
916 …memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
921 …memory region  miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
926 …(USWC) memory region  true miss for the L2 cache with a snoop miss in the other processor module.",
931 …ion  true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
936 …a writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the tim…
941 …a writes to uncacheable write combining (USWC) memory region  outstanding, per cycle, from the tim…
966 …h instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
971 …h instructions miss the L2 cache with a snoop hit in the other processor module, data forwarding i…
976 …prefetch instructions true miss for the L2 cache with a snoop miss in the other processor module.",
981 …ions true miss for the L2 cache with a snoop miss in the other processor module.  Requires MSR_OFF…
986 …s data cache lines requests by software prefetch instructions outstanding, per cycle, from the tim…
991 …s data cache lines requests by software prefetch instructions outstanding, per cycle, from the tim…