Lines Matching full:all
12 "BriefDescription": "All data cache accesses.",
17 "BriefDescription": "All L2 cache accesses.",
18 …r": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l…
36 "MetricExpr": "l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
41 "BriefDescription": "All L2 cache misses.",
42 …etricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
60 "MetricExpr": "l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
65 "BriefDescription": "All L2 cache hits.",
66 "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all",
84 "MetricExpr": "l2_pf_hit_l2.all",
102 "MetricExpr": "(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all",
108 "BriefDescription": "Op cache miss ratio for all fetches.",
114 …"BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will …
144 "BriefDescription": "All L1 data cache fills.",
145 "MetricExpr": "ls_any_fills_from_sys.all",
187 "MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all",
193 "MetricExpr": "bp_l1_tlb_miss_l2_tlb_miss.all",
199 "MetricExpr": "ls_l1_d_tlb_miss.all",
210 "BriefDescription": "All TLBs flushed.",
211 "MetricExpr": "ls_tlb_flush.all",
217 "MetricExpr": "de_src_op_disp.all",
328 "BriefDescription": "Outbound data from all links (local socket).",