x86/amdzen1/cache.json

75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
105     "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
111 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
134     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
140 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheab…
146     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
152 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized non-…
158 …"BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Self-modifying code invalidates.",
164     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus locks.",
170     "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Bus lock response.",
230 …ble request access status (not including L2 Prefetch). Data cache request miss in L2 (all types).",
260 …L2 Prefetch). Instruction cache request miss in L2 and Data cache request miss in L2 (all types).",
266 …g L2 Prefetch). Instruction cache request hit in L2 and Data cache request hit in L2 (all types).",
284 …"BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipelin…
290 …"BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline whi…
303     "BriefDescription": "All L3 Request Types",
324 …"BriefDescription": "L3 Cache Miss Latency. Total cycles for all transactions divided by 16. Ignor…
331     "BriefDescription": "All L3 Miss Request Types. Ignores SliceMask and ThreadMask.",