Lines Matching +full:min +full:- +full:residency
3 "BriefDescription": "C10 residency percent per package",
4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
10 "BriefDescription": "C1 residency percent per core",
11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
17 "BriefDescription": "C2 residency percent per package",
18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
24 "BriefDescription": "C3 residency percent per package",
25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
31 "BriefDescription": "C6 residency percent per core",
32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
38 "BriefDescription": "C6 residency percent per package",
39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
45 "BriefDescription": "C7 residency percent per core",
46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
52 "BriefDescription": "C7 residency percent per package",
53 "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
59 "BriefDescription": "C8 residency percent per package",
60 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
66 "BriefDescription": "C9 residency percent per package",
67 "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
74 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
120 …"MetricExpr": "(tma_info_core_slots - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIR…
130 "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info_core_slots",
173 "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)",
197 …ber of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
199 …cExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEA…
352 "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_RETIRED.COND_TAKEN)",
391 … "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block",
396 "BriefDescription": "Percentage of total non-speculative loads that are splits",
401 …"BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown sto…
461 …ricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEA…
470 …icExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_core_clks - max((MEM_BOUND_STALLS.LOAD - LD_HEA…
503 … "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_info_core_clks + tma_store_bound)",
519 …n": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)",
525 …ounts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This…
561 …alled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not b…
562 …"MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_b…
570 …"MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / tma_info_core_slots…