x86/alderlake/pipeline.json

17 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
295 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address…
328         "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
366 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)",
370 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re…
439 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that…
464 …"BriefDescription": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time bu…
467 …"PublicDescription": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup…
473 …"BriefDescription": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time bu…
476 …"PublicDescription": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup…
546 …stal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread …
754         "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
757 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
772         "BriefDescription": "Number of instructions retired. General Counter - architectural event",
776 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
798         "BriefDescription": "Precise instruction retired with PEBS precise-distribution",
801 …ons Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Cou…
810 …imes as specified by the RCX register. Note the number of iterations is implementation-dependent.",
858 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
880         "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instructions.",
883 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vecto…
889         "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instructions.",
892 …"PublicDescription": "Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vecto…
988 …"PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (F…
998 …iption": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
1008 …": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
1017 …"PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream D…
1050 …ounts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stor…
1074         "BriefDescription": "Self-modifying code (SMC) detected.",
1077 …   "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
1104 …B) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-e…
1118 …ue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the fr…
1121 …ue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the fr…
1127 …"BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
1130 …s in TMA method where no micro-operations were being issued from front-end to back-end of the mach…
1139 …ed due to incorrect speculation. It covers all types of control-flow or data-related mis-speculati…
1148 …specualtive operations that were issued but not retired as well as the out-of-order engine recover…
1162 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
1164 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TM…
1170 …n": "TMA slots available for an unhalted logical processor. General counter - architectural event",
1173 …-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. Th…
1435 …    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
1439 …"PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physic…
1445 …    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
1449 …"PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on phys…
1455 …    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
1459 …"PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on phys…
1465 …    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
1469 …"PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on phys…
1475         "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
1479         "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
1485         "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
1489         "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
1495         "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
1499         "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
1505         "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
1509         "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
1537         "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
1584 …"PublicDescription": "Counts the number of retired micro-operations (uops) except the last uop of …
1599 …tion": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",