Lines Matching full:accesses
37 for cachelines with highest contention - highest number of HITM accesses.
196 - cacheline percentage of all Remote/Local HITM accesses
199 - cacheline percentage of all peer accesses
208 - sum of all cachelines accesses
211 - sum of all load accesses
214 - sum of all store accesses
217 L1Hit - store accesses that hit L1
218 L1Miss - store accesses that missed L1
219 N/A - store accesses with memory level is not available
225 - count of LLC load accesses, includes LLC hits and LLC HITMs
228 - count of remote load accesses, includes remote hits and remote HITMs;
229 on Arm neoverse cores, RmtHit is used to account remote accesses,
233 - count of local and remote DRAM accesses
238 - % of Remote/Local HITM accesses for given offset within cacheline
241 - % of Remote/Local peer accesses for given offset within cacheline
244 - % of store accesses that hit L1, missed L1 and N/A (no available) memory
251 - pid of the process responsible for the accesses
254 - tid of the process responsible for the accesses
257 - code address responsible for the accesses
260 - sum of cycles for given accesses - Remote/Local HITM and generic load
263 - sum of cycles for given accesses - Remote/Local peer load and generic load
282 The 'Node' field displays nodes that accesses given cacheline
315 - overall statistics of memory accesses