x86/kcpuid/cpuid.csv

22          1,    0,  ECX,      2, dtes64, DS area uses 64-bit layout
26          1,    0,  ECX,      6, smx, Safer Mode Extension supported
33          1,    0,  ECX,     13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported
36          1,    0,  ECX,     17, pcid, Process-Context Identifiers feature present
43 …1,    0,  ECX,     24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline …
48          1,    0,  ECX,     29, f16c, 16-bit floating-point conversion instruction supported
52          1,    0,  EDX,      1, vme, Virtual-8086 Mode Enhancement
67          1,    0,  EDX,     17, pse36, 36-Bit Page Size Extension
103          4,    0,  ECX,   31:0, cache_sets, Number of Sets - 1
104 … 1 means WBINVD/INVD is not ganranteed to act upon lower level caches of non-originating threads s…
112 	 5,    0,  ECX,      0, mwait_ext, Enum of Monitor-Mwait extensions supported
114 	 5,    0,  EDX,    3:0, c0_sub_stats, Number of C0* sub C-states supported using MWAIT
115 	 5,    0,  EDX,    7:4, c1_sub_stats, Number of C1* sub C-states supported using MWAIT
116 	 5,    0,  EDX,   11:8, c2_sub_stats, Number of C2* sub C-states supported using MWAIT
117 	 5,    0,  EDX,  15:12, c3_sub_stats, Number of C3* sub C-states supported using MWAIT
118 	 5,    0,  EDX,  19:16, c4_sub_stats, Number of C4* sub C-states supported using MWAIT
119 	 5,    0,  EDX,  23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT
120 	 5,    0,  EDX,  27:24, c6_sub_stats, Number of C6* sub C-states supported using MWAIT
121 	 5,    0,  EDX,  31:28, c7_sub_stats, Number of C7* sub C-states supported using MWAIT
131 	 6,    0,  EAX,      5, ecmd, Clock modulation duty cycle extension supported
150 	 6,    0,  ECX,      3, energ_bias, Performance-energy bias preference supported
154 # AVX512 refers to https://en.wikipedia.org/wiki/AVX-512
164 	 7,    0,  EBX,      7, smep, Supervisor-Mode Execution Prevention
191 	 7,    0,  ECX,      2, umip, User-mode Instruction Prevention
193 	 7,    0,  ECX,      3, pku, Protection Keys for User-mode pages
196 …,  ECX,  21:17, mawau, The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode
217        0xA,    0,  EAX,   15:8, pmu_gp_cnt_num, Numer of general-purose PMU counters per logical CPU
224        0xA,    0,  EBX,      3, pmu_no_llc_ref_evt, Last-level cache reference event not available
225        0xA,    0,  EBX,      4, pmu_no_llc_mis_evt, Last-level cache misses event not available
238        0xB,    0,  ECX,   15:8, lvl_type, 0-Invalid 1-SMT 2-Core
249        0xD,    0,  EAX,    7:5, avx512, AVX-512 state
270 …0xF,    0,  EBX,   31:0, rmid_range, Maximum range (zero-based) of RMID within this physical proce…
273        0xF,    1,  ECX,   31:0, rmid_range, Maximum range (zero-based) of RMID of this types
314 # System-On-Chip Vendor Attribute
316       0x17,    0,  EAX,   31:0, max_socid, Maximum input value of supported sub-leaf
317       0x17,    0,  EBX,   15:0, soc_vid, SOC Vendor ID
318       0x17,    0,  EBX,     16, std_vid, SOC Vendor ID is assigned via an industry standard scheme
319       0x17,    0,  ECX,   31:0, soc_pid, SOC Project ID assigned by vendor
333       0x1A,    0,  EAX,  31:24, core_type, 20H-Intel_Atom 40H-Intel_Core
337 # V2 Extended Topology - A preferred superset to leaf 0BH
341 # 40000000H - 4FFFFFFFH is invalid range
354 0x80000001,    0,  ECX,      0, lahf_lm, LAHF/SAHF available in 64-bit mode
355 0x80000001,    0,  ECX,      1, cmplegacy, Core multi-processing legacy mode
363 0x80000001,    0,  ECX,      9, osvw, OS Visible Work-around support
369 0x80000001,    0,  ECX,     16, fma4, Four-operand FMA instruction support
370 0x80000001,    0,  ECX,     17, tce, Translation cache extension
372 0x80000001,    0,  ECX,     23, perfctrextcore, Indicates support for Core::X86::Msr::PERF_CTL0 - 5…
375 0x80000001,    0,  ECX,     27, perftsc, Performance time-stamp counter supported
378 0x80000001,    0,  ECX,     30, admskextn, Indicates support for address mask extension (to 32 bits…
380 0x80000001,    0,  EDX,      0, fpu, x87 floating point unit on-chip
381 0x80000001,    0,  EDX,      1, vme, Virtual-mode enhancements
383 0x80000001,    0,  EDX,      3, pse, Page-size extensions (4 MB pages)
385 0x80000001,    0,  EDX,      5, msr, Model-specific registers (MSRs), with RDMSR and WRMSR instruct…
386 0x80000001,    0,  EDX,      6, pae, Physical-address extensions (PAE)
391 0x80000001,    0,  EDX,     12, mtrr, Memory-type range registers
392 0x80000001,    0,  EDX,     13, pge, Page global extension, CR4.PGE
396 0x80000001,    0,  EDX,     17, pse36, Page-size extensions
448 0x8000001F,	0, EBX,    5:0, c-bit, Page table bit number used to enable memory encryption
450 0x8000001F,	0, ECX,   31:0, num_encrypted_guests, Maximum ASID value that may be used for an SEV-en…
451 …0, minimum_sev_asid, Minimum ASID value that must be used for an SEV-enabled, SEV-ES-disabled guest