215 	u32 reg_val_GCR;  in setup_bitclk()  local
222 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in setup_bitclk()
223 	writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);  in setup_bitclk()
261 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in setup_bitclk()
262 	writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);  in setup_bitclk()
350 	u32 reg_val_DMACR, reg_val_GCR;  in enable_msp()  local
373 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in enable_msp()
374 	writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);  in enable_msp()
381 	u32 reg_val_GCR, reg_val_FLR;  in flush_fifo_rx()  local
384 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in flush_fifo_rx()
385 	writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);  in flush_fifo_rx()
393 	writel(reg_val_GCR, msp->registers + MSP_GCR);  in flush_fifo_rx()
398 	u32 reg_val_GCR, reg_val_FLR;  in flush_fifo_tx()  local
401 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in flush_fifo_tx()
402 	writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);  in flush_fifo_tx()
411 	writel(reg_val_GCR, msp->registers + MSP_GCR);  in flush_fifo_tx()
486 	u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;  in disable_msp_rx()  local
488 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in disable_msp_rx()
489 	writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);  in disable_msp_rx()
502 	u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;  in disable_msp_tx()  local
504 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in disable_msp_tx()
505 	writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);  in disable_msp_tx()
518 	u32 reg_val_GCR;  in disable_msp()  local
521 	reg_val_GCR = readl(msp->registers + MSP_GCR);  in disable_msp()
525 		reg_val_GCR = readl(msp->registers + MSP_GCR);  in disable_msp()
526 		writel(reg_val_GCR | LOOPBACK_MASK,  in disable_msp()
556 	u32 reg_val_GCR, enable_bit;  in ux500_msp_i2s_trigger()  local
572 		reg_val_GCR = readl(msp->registers + MSP_GCR);  in ux500_msp_i2s_trigger()
573 		writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);  in ux500_msp_i2s_trigger()