soc/ti/davinci-mcasp.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
7  * Author: Nirmal Pandey <n-pandey@ti.com>,
70 /* Left(even TDM Slot) Channel Status Register File */
72 /* Right(odd TDM slot) Channel Status Register File */
74 /* Left(even TDM slot) User Data Register File */
76 /* Right(odd TDM Slot) User Data Register File */
100  * DAVINCI_MCASP_PWREMUMGT_REG - Power Down and Emulation Management
107  * DAVINCI_MCASP_PFUNC_REG - Pin Function / GPIO Enable Register Bits
108  * DAVINCI_MCASP_PDIR_REG - Pin Direction Register Bits
109  * DAVINCI_MCASP_PDOUT_REG - Pin output in GPIO mode
110  * DAVINCI_MCASP_PDSET_REG - Pin input in GPIO mode
122  * DAVINCI_MCASP_TXDITCTL_REG - Transmit DIT Control Register Bits
124 #define DITEN	BIT(0)	/* Transmit DIT mode enable/disable */
129  * DAVINCI_MCASP_TXFMT_REG - Transmit Bitstream Format Register Bits
140  * DAVINCI_MCASP_RXFMT_REG - Receive Bitstream Format Register Bits
151  * DAVINCI_MCASP_TXFMCTL_REG -  Transmit Frame Control Register Bits
159  * DAVINCI_MCASP_RXFMCTL_REG - Receive Frame Control Register Bits
167  * DAVINCI_MCASP_ACLKXCTL_REG - Transmit Clock Control Register Bits
185  * DAVINCI_MCASP_AHCLKXCTL_REG - High Frequency Transmit Clock Control
194  * DAVINCI_MCASP_AHCLKRCTL_REG - High Frequency Receive Clock Control
203  * DAVINCI_MCASP_XRSRCTL_BASE_REG -  Serializer Control Register Bits
205 #define MODE(val)	(val)  macro
217  * DAVINCI_MCASP_LBCTL_REG - Loop Back Control Register Bits
224  * DAVINCI_MCASP_TXTDMSLOT_REG - Transmit TDM Slot Register configuration
229  * DAVINCI_MCASP_RXTDMSLOT_REG - Receive TDM Slot Register configuration
234  * DAVINCI_MCASP_GBLCTL_REG -  Global Control Register Bits
240 #define RXFSRST		BIT(4)	/* Frame Sync Generator Reset */
245 #define TXFSRST		BIT(12)	/* Frame Sync Generator Reset */
248  * DAVINCI_MCASP_TXSTAT_REG - Transmitter Status Register Bits
249  * DAVINCI_MCASP_RXSTAT_REG - Receiver Status Register Bits
255  * DAVINCI_MCASP_AMUTE_REG -  Mute Control Register Bits
271  * DAVINCI_MCASP_REVTCTL_REG - Receiver DMA Event Control Register bits
276  * DAVINCI_MCASP_XEVTCTL_REG - Transmitter DMA Event Control Register bits
281  * DAVINCI_MCASP_EVTCTLR_REG - Receiver Interrupt Control Register Bits
286  * DAVINCI_MCASP_EVTCTLX_REG - Transmitter Interrupt Control Register Bits
291  * DAVINCI_MCASP_W[R]FIFOCTL - Write/Read FIFO Control Register bits
298 /* Source of High-frequency transmit/receive clock */