Lines Matching +full:0 +full:xfffff
19 #define TEGRA20_SPDIF_CTRL 0x0
20 #define TEGRA20_SPDIF_STATUS 0x4
21 #define TEGRA20_SPDIF_STROBE_CTRL 0x8
22 #define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C
23 #define TEGRA20_SPDIF_DATA_OUT 0x40
24 #define TEGRA20_SPDIF_DATA_IN 0x80
25 #define TEGRA20_SPDIF_CH_STA_RX_A 0x100
26 #define TEGRA20_SPDIF_CH_STA_RX_B 0x104
27 #define TEGRA20_SPDIF_CH_STA_RX_C 0x108
28 #define TEGRA20_SPDIF_CH_STA_RX_D 0x10C
29 #define TEGRA20_SPDIF_CH_STA_RX_E 0x110
30 #define TEGRA20_SPDIF_CH_STA_RX_F 0x114
31 #define TEGRA20_SPDIF_CH_STA_TX_A 0x140
32 #define TEGRA20_SPDIF_CH_STA_TX_B 0x144
33 #define TEGRA20_SPDIF_CH_STA_TX_C 0x148
34 #define TEGRA20_SPDIF_CH_STA_TX_D 0x14C
35 #define TEGRA20_SPDIF_CH_STA_TX_E 0x150
36 #define TEGRA20_SPDIF_CH_STA_TX_F 0x154
37 #define TEGRA20_SPDIF_USR_STA_RX_A 0x180
38 #define TEGRA20_SPDIF_USR_DAT_TX_A 0x1C0
42 /* Start capturing from 0=right, 1=left channel */
92 * 0 = Single data (16 bit needs to be padded to match the
104 #define TEGRA20_SPDIF_BIT_MODE_16BIT 0
166 /* Preamble status: 0=Preamble OK, 1=bad/missing preamble */
169 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
174 * 0=entire block not recieved yet.
179 /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
184 * 1=attention level reached, 0=attention level not reached.
190 * 1=attention level reached, 0=attention level not reached.
196 * 1=attention level reached, 0=attention level not reached.
202 * 1=attention level reached, 0=attention level not reached.
213 #define TEGRA20_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA20_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
215 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
223 #define TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA20_SPDIF_STROBE_CTRL_DATA_STROBE…
229 #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0
230 #define TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA20_SPDIF_STROBE_CTRL_CLOCK_PERIO…
237 #define TEGRA20_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0
245 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
257 #define TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RU_FUL…
265 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
277 #define TEGRA20_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUN…
282 #define TEGRA20_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0
290 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
302 #define TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA20_SPDIF_DATA_FIFO_CSR_RX_FUL…
310 (0x3 << TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
321 #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0
322 #define TEGRA20_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUN…
328 * 16-bit (BIT_MODE=00, PACK=0)
329 * 20-bit (BIT_MODE=01, PACK=0)
330 * 24-bit (BIT_MODE=10, PACK=0)
331 * raw (BIT_MODE=11, PACK=0)
335 #define TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT 0
336 #define TEGRA20_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_SHIFT)
338 #define TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT 0
339 #define TEGRA20_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_20_SHIFT)
341 #define TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT 0
342 #define TEGRA20_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_OUT_DATA_24_SHIFT)
350 #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_DATA…
353 #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT)
355 #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0
356 #define TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_OUT_DATA_RAW_PREA…
359 #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_…
361 #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0
362 #define TEGRA20_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_OUT_DATA_16_…
368 * 16-bit (BIT_MODE=00, PACK=0)
369 * 20-bit (BIT_MODE=01, PACK=0)
370 * 24-bit (BIT_MODE=10, PACK=0)
371 * raw (BIT_MODE=11, PACK=0)
383 #define TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT)
385 #define TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT 0
386 #define TEGRA20_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_SHIFT)
388 #define TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT 0
389 #define TEGRA20_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_20_SHIFT)
391 #define TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT 0
392 #define TEGRA20_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA20_SPDIF_DATA_IN_DATA_24_SHIFT)
395 #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA20_SPDIF_DATA_IN_DATA_RAW_DATA_S…
398 #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT)
400 #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0
401 #define TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA20_SPDIF_DATA_IN_DATA_RAW_PREAMB…
404 #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_P…
406 #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0
407 #define TEGRA20_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA20_SPDIF_DATA_IN_DATA_16_PA…