Lines Matching +full:tx +full:- +full:threshold
1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
74 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
84 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
85 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
95 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
102 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
104 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
107 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
110 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
114 regmap_write(asrc->regmap, in tegra186_asrc_runtime_resume()
117 asrc->lane[id].int_part); in tegra186_asrc_runtime_resume()
119 regmap_write(asrc->regmap, in tegra186_asrc_runtime_resume()
122 asrc->lane[id].frac_part); in tegra186_asrc_runtime_resume()
150 return -EINVAL; in tegra186_asrc_set_audio_cif()
158 tegra_set_cif(asrc->regmap, reg, &cif_conf); in tegra186_asrc_set_audio_cif()
167 struct device *dev = dai->dev; in tegra186_asrc_in_hw_params()
169 int ret, id = dai->id; in tegra186_asrc_in_hw_params()
171 /* Set input threshold */ in tegra186_asrc_in_hw_params()
172 regmap_write(asrc->regmap, in tegra186_asrc_in_hw_params()
173 ASRC_STREAM_REG(TEGRA186_ASRC_RX_THRESHOLD, dai->id), in tegra186_asrc_in_hw_params()
174 asrc->lane[id].input_thresh); in tegra186_asrc_in_hw_params()
177 ASRC_STREAM_REG(TEGRA186_ASRC_RX_CIF_CTRL, dai->id)); in tegra186_asrc_in_hw_params()
179 dev_err(dev, "Can't set ASRC RX%d CIF: %d\n", dai->id, ret); in tegra186_asrc_in_hw_params()
190 struct device *dev = dai->dev; in tegra186_asrc_out_hw_params()
192 int ret, id = dai->id - 7; in tegra186_asrc_out_hw_params()
194 /* Set output threshold */ in tegra186_asrc_out_hw_params()
195 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
197 asrc->lane[id].output_thresh); in tegra186_asrc_out_hw_params()
202 dev_err(dev, "Can't set ASRC TX%d CIF: %d\n", id, ret); in tegra186_asrc_out_hw_params()
207 if (asrc->lane[id].hwcomp_disable) { in tegra186_asrc_out_hw_params()
208 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
213 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
218 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
224 regmap_update_bits(asrc->regmap, in tegra186_asrc_out_hw_params()
226 1, asrc->lane[id].ratio_source); in tegra186_asrc_out_hw_params()
228 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_SW) { in tegra186_asrc_out_hw_params()
229 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
231 asrc->lane[id].int_part); in tegra186_asrc_out_hw_params()
232 regmap_write(asrc->regmap, in tegra186_asrc_out_hw_params()
234 asrc->lane[id].frac_part); in tegra186_asrc_out_hw_params()
245 (struct soc_enum *)kcontrol->private_value; in tegra186_asrc_get_ratio_source()
248 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_source()
250 ucontrol->value.enumerated.item[0] = asrc->lane[id].ratio_source; in tegra186_asrc_get_ratio_source()
259 (struct soc_enum *)kcontrol->private_value; in tegra186_asrc_put_ratio_source()
262 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_source()
265 asrc->lane[id].ratio_source = ucontrol->value.enumerated.item[0]; in tegra186_asrc_put_ratio_source()
267 regmap_update_bits_check(asrc->regmap, asrc_private->reg, in tegra186_asrc_put_ratio_source()
269 asrc->lane[id].ratio_source, in tegra186_asrc_put_ratio_source()
279 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_ratio_int()
282 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_int()
284 regmap_read(asrc->regmap, in tegra186_asrc_get_ratio_int()
286 &asrc->lane[id].int_part); in tegra186_asrc_get_ratio_int()
288 ucontrol->value.integer.value[0] = asrc->lane[id].int_part; in tegra186_asrc_get_ratio_int()
297 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_ratio_int()
300 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_int()
303 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) { in tegra186_asrc_put_ratio_int()
304 dev_err(cmpnt->dev, in tegra186_asrc_put_ratio_int()
307 return -EINVAL; in tegra186_asrc_put_ratio_int()
310 asrc->lane[id].int_part = ucontrol->value.integer.value[0]; in tegra186_asrc_put_ratio_int()
312 regmap_update_bits_check(asrc->regmap, in tegra186_asrc_put_ratio_int()
316 asrc->lane[id].int_part, &change); in tegra186_asrc_put_ratio_int()
327 (struct soc_mreg_control *)kcontrol->private_value; in tegra186_asrc_get_ratio_frac()
330 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_ratio_frac()
332 regmap_read(asrc->regmap, in tegra186_asrc_get_ratio_frac()
334 &asrc->lane[id].frac_part); in tegra186_asrc_get_ratio_frac()
336 ucontrol->value.integer.value[0] = asrc->lane[id].frac_part; in tegra186_asrc_get_ratio_frac()
345 (struct soc_mreg_control *)kcontrol->private_value; in tegra186_asrc_put_ratio_frac()
348 unsigned int id = asrc_private->regbase / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_ratio_frac()
351 if (asrc->lane[id].ratio_source == TEGRA186_ASRC_RATIO_SOURCE_ARAD) { in tegra186_asrc_put_ratio_frac()
352 dev_err(cmpnt->dev, in tegra186_asrc_put_ratio_frac()
355 return -EINVAL; in tegra186_asrc_put_ratio_frac()
358 asrc->lane[id].frac_part = ucontrol->value.integer.value[0]; in tegra186_asrc_put_ratio_frac()
360 regmap_update_bits_check(asrc->regmap, in tegra186_asrc_put_ratio_frac()
364 asrc->lane[id].frac_part, &change); in tegra186_asrc_put_ratio_frac()
375 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_hwcomp_disable()
378 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_hwcomp_disable()
380 ucontrol->value.integer.value[0] = asrc->lane[id].hwcomp_disable; in tegra186_asrc_get_hwcomp_disable()
389 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_hwcomp_disable()
392 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_hwcomp_disable()
393 int value = ucontrol->value.integer.value[0]; in tegra186_asrc_put_hwcomp_disable()
395 if (value == asrc->lane[id].hwcomp_disable) in tegra186_asrc_put_hwcomp_disable()
398 asrc->lane[id].hwcomp_disable = value; in tegra186_asrc_put_hwcomp_disable()
407 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_input_threshold()
410 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_input_threshold()
412 ucontrol->value.integer.value[0] = (asrc->lane[id].input_thresh & 0x3); in tegra186_asrc_get_input_threshold()
421 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_input_threshold()
424 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_input_threshold()
425 int value = (asrc->lane[id].input_thresh & ~(0x3)) | in tegra186_asrc_put_input_threshold()
426 ucontrol->value.integer.value[0]; in tegra186_asrc_put_input_threshold()
428 if (value == asrc->lane[id].input_thresh) in tegra186_asrc_put_input_threshold()
431 asrc->lane[id].input_thresh = value; in tegra186_asrc_put_input_threshold()
440 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_get_output_threshold()
443 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_get_output_threshold()
445 ucontrol->value.integer.value[0] = (asrc->lane[id].output_thresh & 0x3); in tegra186_asrc_get_output_threshold()
454 (struct soc_mixer_control *)kcontrol->private_value; in tegra186_asrc_put_output_threshold()
457 unsigned int id = asrc_private->reg / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_put_output_threshold()
458 int value = (asrc->lane[id].output_thresh & ~(0x3)) | in tegra186_asrc_put_output_threshold()
459 ucontrol->value.integer.value[0]; in tegra186_asrc_put_output_threshold()
461 if (value == asrc->lane[id].output_thresh) in tegra186_asrc_put_output_threshold()
464 asrc->lane[id].output_thresh = value; in tegra186_asrc_put_output_threshold()
472 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); in tegra186_asrc_widget_event()
473 struct tegra186_asrc *asrc = dev_get_drvdata(cmpnt->dev); in tegra186_asrc_widget_event()
475 (w->reg - TEGRA186_ASRC_ENABLE) / TEGRA186_ASRC_STREAM_STRIDE; in tegra186_asrc_widget_event()
477 regmap_write(asrc->regmap, in tegra186_asrc_widget_event()
494 .name = "ASRC-RX-CIF"#id, \
496 .stream_name = "RX" #id "-CIF-Playback",\
506 .stream_name = "RX" #id "-CIF-Capture", \
520 .name = "ASRC-TX-CIF"#id, \
522 .stream_name = "TX" #id "-CIF-Playback",\
532 .stream_name = "TX" #id "-CIF-Capture", \
611 { "RX" #id " XBAR-" sname, NULL, "RX" #id " XBAR-TX" }, \
612 { "RX" #id "-CIF-" sname, NULL, "RX" #id " XBAR-" sname }, \
613 { "RX" #id, NULL, "RX" #id "-CIF-" sname }, \
614 { "TX" #id, NULL, "RX" #id }, \
615 { "TX" #id "-CIF-" sname, NULL, "TX" #id }, \
616 { "TX" #id " XBAR-" sname, NULL, "TX" #id "-CIF-" sname }, \
617 { "TX" #id " XBAR-RX", NULL, "TX" #id " XBAR-" sname },
624 { "RX7 XBAR-" sname, NULL, "RX7 XBAR-TX" }, \
625 { "RX7-CIF-" sname, NULL, "RX7 XBAR-" sname }, \
626 { "RX7", NULL, "RX7-CIF-" sname }, \
807 /* Input threshold for watermark fields */
808 SOC_SINGLE_EXT("Stream1 Input Threshold",
813 SOC_SINGLE_EXT("Stream2 Input Threshold",
818 SOC_SINGLE_EXT("Stream3 Input Threshold",
823 SOC_SINGLE_EXT("Stream4 Input Threshold",
828 SOC_SINGLE_EXT("Stream5 Input Threshold",
833 SOC_SINGLE_EXT("Stream6 Input Threshold",
838 /* Output threshold for watermark fields */
839 SOC_SINGLE_EXT("Stream1 Output Threshold",
844 SOC_SINGLE_EXT("Stream2 Output Threshold",
849 SOC_SINGLE_EXT("Stream3 Output Threshold",
854 SOC_SINGLE_EXT("Stream4 Output Threshold",
859 SOC_SINGLE_EXT("Stream5 Output Threshold",
864 SOC_SINGLE_EXT("Stream6 Output Threshold",
959 { .compatible = "nvidia,tegra186-asrc" },
966 struct device *dev = &pdev->dev; in tegra186_asrc_platform_probe()
974 return -ENOMEM; in tegra186_asrc_platform_probe()
982 asrc->regmap = devm_regmap_init_mmio(dev, regs, in tegra186_asrc_platform_probe()
984 if (IS_ERR(asrc->regmap)) { in tegra186_asrc_platform_probe()
986 return PTR_ERR(asrc->regmap); in tegra186_asrc_platform_probe()
989 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_platform_probe()
991 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_CFG, in tegra186_asrc_platform_probe()
996 asrc->lane[i].ratio_source = TEGRA186_ASRC_RATIO_SOURCE_SW; in tegra186_asrc_platform_probe()
997 asrc->lane[i].int_part = 1; in tegra186_asrc_platform_probe()
998 asrc->lane[i].frac_part = 0; in tegra186_asrc_platform_probe()
999 asrc->lane[i].hwcomp_disable = 0; in tegra186_asrc_platform_probe()
1000 asrc->lane[i].input_thresh = in tegra186_asrc_platform_probe()
1002 asrc->lane[i].output_thresh = in tegra186_asrc_platform_probe()
1021 pm_runtime_disable(&pdev->dev); in tegra186_asrc_platform_remove()
1033 .name = "tegra186-asrc",