soc/sprd/sprd-pcm-compress.c

28 /* Stage 0 IRAM buffer size definition */
58  * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
59  * power-on) and DDR buffer. The source channel will transfer data from IRAM
60  * buffer to the DSP fifo to decoding/encoding, once IRAM buffer is empty by
62  * DDR buffer to IRAM buffer.
64  * Since the DSP fifo is only 512B, IRAM buffer is allocated by 32K, and DDR
65  * buffer is larger to 2M. That means only the IRAM 32k data is transferred
66  * done, we can wake up the AP system to transfer data from DDR to IRAM, and
77 	/* Stage 0 IRAM buffer */
82 	/* DSP play information IRAM buffer */
87 	/* Data size copied to IRAM buffer */
91 	/* Stage 0 IRAM buffer received data size */
121 	/* Update data size copied to IRAM buffer */  in sprd_platform_compr_dma_complete()
339 	 * Allocate the stage 0 IRAM buffer size, including the DMA 0  in sprd_platform_compr_open()
539 	 * We usually set fragment size as 32K, and the stage 0 IRAM buffer  in sprd_platform_compr_copy()
541 	 * IRAM buffer is less than 32K, that means we have some available  in sprd_platform_compr_copy()
542 	 * spaces for the stage 0 IRAM buffer.  in sprd_platform_compr_copy()
550 			 * Copy data to the stage 0 IRAM buffer directly if  in sprd_platform_compr_copy()
562 			 * of the stage 0 IRAM buffer, we should copy one  in sprd_platform_compr_copy()
563 			 * partial data to the stage 0 IRAM buffer, and copy  in sprd_platform_compr_copy()
577 	 * Copy data to the stage 1 DDR buffer if no spaces for the stage 0 IRAM  in sprd_platform_compr_copy()