27 #define BDW_DSP_BAR 0  macro
60 	{"dmac0", BDW_DSP_BAR, DMAC0_OFFSET, DMAC_SIZE,
62 	{"dmac1", BDW_DSP_BAR, DMAC1_OFFSET, DMAC_SIZE,
64 	{"ssp0", BDW_DSP_BAR, SSP0_OFFSET, SSP_SIZE,
66 	{"ssp1", BDW_DSP_BAR, SSP1_OFFSET, SSP_SIZE,
68 	{"iram", BDW_DSP_BAR, IRAM_OFFSET, BDW_IRAM_SIZE,
70 	{"dram", BDW_DSP_BAR, DRAM_OFFSET, BDW_DRAM_SIZE,
72 	{"shim", BDW_DSP_BAR, SHIM_OFFSET, SHIM_SIZE,
86 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,  in bdw_run()
91 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_run()
101 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_reset()
109 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_reset()
151 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CSR,  in bdw_set_dsp_D0()
156 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  in bdw_set_dsp_D0()
163 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_CLKCTL,  in bdw_set_dsp_D0()
196 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  SHIM_CSR2,  in bdw_set_dsp_D0()
201 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_HMDC,  in bdw_set_dsp_D0()
208 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRX,  in bdw_set_dsp_D0()
210 	snd_sof_dsp_update_bits(sdev, BDW_DSP_BAR, SHIM_IMRD,  in bdw_set_dsp_D0()
215 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, 0x0);  in bdw_set_dsp_D0()
216 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCD, 0x0);  in bdw_set_dsp_D0()
217 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0x80, 0x6);  in bdw_set_dsp_D0()
218 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, 0xe0, 0x300a);  in bdw_set_dsp_D0()
257 	status = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);  in bdw_dump()
258 	panic = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);  in bdw_dump()
265 	imrx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRX);  in bdw_dump()
266 	imrd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IMRD);  in bdw_dump()
296 	isr = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_ISRX);  in bdw_irq_handler()
308 	imrx = snd_sof_dsp_read64(sdev, BDW_DSP_BAR, SHIM_IMRX);  in bdw_irq_thread()
309 	ipcx = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCX);  in bdw_irq_thread()
315 		snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  in bdw_irq_thread()
335 	ipcd = snd_sof_dsp_read(sdev, BDW_DSP_BAR, SHIM_IPCD);  in bdw_irq_thread()
341 		snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR,  in bdw_irq_thread()
368 	snd_sof_dsp_write(sdev, BDW_DSP_BAR, SHIM_IPCX, SHIM_IPCX_BUSY);  in bdw_send_msg()
386 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCD,  in bdw_host_done()
391 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,  in bdw_host_done()
398 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IPCX,  in bdw_dsp_done()
402 	snd_sof_dsp_update_bits_unlocked(sdev, BDW_DSP_BAR, SHIM_IMRX,  in bdw_dsp_done()
441 	sdev->bar[BDW_DSP_BAR] = devm_ioremap(sdev->dev, base, size);  in bdw_probe()
442 	if (!sdev->bar[BDW_DSP_BAR]) {  in bdw_probe()
448 	dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BDW_DSP_BAR]);  in bdw_probe()
451 	sdev->mmio_bar = BDW_DSP_BAR;  in bdw_probe()
452 	sdev->mailbox_bar = BDW_DSP_BAR;  in bdw_probe()