Lines Matching +full:min +full:- +full:sample +full:- +full:rate +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
50 (i < adg->clkin_size) && \
51 ((pos) = adg->clkin[i]); \
55 (i < adg->clkout_size) && \
56 ((pos) = adg->clkout[i]); \
58 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
85 for (i = 3; i >= 0; i--) { in rsnd_adg_calculate_brgx()
88 return (u32)((i << 8) | ((div / ratio) - 1)); in rsnd_adg_calculate_brgx()
129 unsigned int min, diff; in __rsnd_adg_get_timesel_ratio() local
131 adg->clkin_rate[CLKA], /* 0000: CLKA */ in __rsnd_adg_get_timesel_ratio()
132 adg->clkin_rate[CLKB], /* 0001: CLKB */ in __rsnd_adg_get_timesel_ratio()
133 adg->clkin_rate[CLKC], /* 0010: CLKC */ in __rsnd_adg_get_timesel_ratio()
134 adg->brg_rate[ADG_HZ_441], /* 0011: BRGA */ in __rsnd_adg_get_timesel_ratio()
135 adg->brg_rate[ADG_HZ_48], /* 0100: BRGB */ in __rsnd_adg_get_timesel_ratio()
138 min = ~0; in __rsnd_adg_get_timesel_ratio()
150 diff = abs(target_rate - sel_rate[sel] / div); in __rsnd_adg_get_timesel_ratio()
151 if (min > diff) { in __rsnd_adg_get_timesel_ratio()
153 min = diff; in __rsnd_adg_get_timesel_ratio()
171 if (min == ~0) { in __rsnd_adg_get_timesel_ratio()
201 if (runtime->rate != in_rate) { in rsnd_adg_get_timesel_ratio()
204 } else if (runtime->rate != out_rate) { in rsnd_adg_get_timesel_ratio()
303 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) in rsnd_adg_clk_query() argument
320 if (rate == adg->clkin_rate[i]) in rsnd_adg_clk_query()
326 if (rate == adg->brg_rate[ADG_HZ_441]) in rsnd_adg_clk_query()
329 if (rate == adg->brg_rate[ADG_HZ_48]) in rsnd_adg_clk_query()
332 return -EIO; in rsnd_adg_clk_query()
342 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) in rsnd_adg_ssi_clk_try_start() argument
351 data = rsnd_adg_clk_query(priv, rate); in rsnd_adg_ssi_clk_try_start()
357 if (0 == (rate % 8000)) in rsnd_adg_ssi_clk_try_start()
360 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); in rsnd_adg_ssi_clk_try_start()
364 (ckr) ? adg->brg_rate[ADG_HZ_48] : in rsnd_adg_ssi_clk_try_start()
365 adg->brg_rate[ADG_HZ_441]); in rsnd_adg_ssi_clk_try_start()
378 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr); in rsnd_adg_clk_control()
379 rsnd_mod_write(adg_mod, BRRA, adg->brga); in rsnd_adg_clk_control()
380 rsnd_mod_write(adg_mod, BRRB, adg->brgb); in rsnd_adg_clk_control()
392 adg->clkin_rate[i] = clk_get_rate(clk); in rsnd_adg_clk_control()
417 struct rsnd_adg *adg = priv->adg; in rsnd_adg_null_clk_get()
419 if (!adg->null_clk) { in rsnd_adg_null_clk_get()
422 adg->null_clk = rsnd_adg_create_null_clk(priv, name, NULL); in rsnd_adg_null_clk_get()
425 return adg->null_clk; in rsnd_adg_null_clk_get()
430 struct rsnd_adg *adg = priv->adg; in rsnd_adg_null_clk_clean()
432 if (adg->null_clk) in rsnd_adg_null_clk_clean()
433 clk_unregister_fixed_rate(adg->null_clk); in rsnd_adg_null_clk_clean()
438 struct rsnd_adg *adg = priv->adg; in rsnd_adg_get_clkin()
460 adg->clkin[i] = clk; in rsnd_adg_get_clkin()
463 adg->clkin_size = clkin_size; in rsnd_adg_get_clkin()
472 return -EIO; in rsnd_adg_get_clkin()
477 struct rsnd_adg *adg = priv->adg; in rsnd_adg_unregister_clkout()
487 struct rsnd_adg *adg = priv->adg; in rsnd_adg_get_clkout()
490 struct device_node *np = dev->of_node; in rsnd_adg_get_clkout()
514 * this means all clkout0/1/2/3 will be same rate in rsnd_adg_get_clkout()
516 prop = of_find_property(np, "clock-frequency", NULL); in rsnd_adg_get_clkout()
520 req_size = prop->length / sizeof(u32); in rsnd_adg_get_clkout()
522 dev_err(dev, "too many clock-frequency\n"); in rsnd_adg_get_clkout()
523 return -EINVAL; in rsnd_adg_get_clkout()
526 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); in rsnd_adg_get_clkout()
540 * SSI itself can divide parent clock by 1/1 - 1/16 in rsnd_adg_get_clkout()
549 * clk_i (internal clock) can't create accurate rate, it will be approximate rate. in rsnd_adg_get_clkout()
553 * clk_i needs x2 of required maximum rate. in rsnd_adg_get_clkout()
555 * - Minimum division of BRRA/BRRB in rsnd_adg_get_clkout()
556 * - rsnd_ssi_clk_query() in rsnd_adg_get_clkout()
558 * Sample Settings for TDM 8ch, 32bit width in rsnd_adg_get_clkout()
560 * 8(ch) x 32(bit) x 44100(Hz) x 2<Note> = 22579200 in rsnd_adg_get_clkout()
561 * 8(ch) x 32(bit) x 48000(Hz) x 2<Note> = 24576000 in rsnd_adg_get_clkout()
563 * clock-frequency = <22579200 24576000>; in rsnd_adg_get_clkout()
566 u32 rate, div; in rsnd_adg_get_clkout() local
568 rate = clk_get_rate(clk); in rsnd_adg_get_clkout()
570 if (0 == rate) /* not used */ in rsnd_adg_get_clkout()
577 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_441]) * req_Hz[ADG_HZ_441]; in rsnd_adg_get_clkout()
578 if (!adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441] && (0 == rate % 44100)) { in rsnd_adg_get_clkout()
579 div = rate / req_Hz[ADG_HZ_441]; in rsnd_adg_get_clkout()
583 adg->brg_rate[ADG_HZ_441] = rate / div; in rsnd_adg_get_clkout()
596 rate = (clk_get_rate(clk) / req_Hz[ADG_HZ_48]) * req_Hz[ADG_HZ_48]; in rsnd_adg_get_clkout()
597 if (!adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48] && (0 == rate % 48000)) { in rsnd_adg_get_clkout()
598 div = rate / req_Hz[ADG_HZ_48]; in rsnd_adg_get_clkout()
602 adg->brg_rate[ADG_HZ_48] = rate / div; in rsnd_adg_get_clkout()
612 if (!(adg->brg_rate[ADG_HZ_48] && req_Hz[ADG_HZ_48]) && in rsnd_adg_get_clkout()
613 !(adg->brg_rate[ADG_HZ_441] && req_Hz[ADG_HZ_441])) in rsnd_adg_get_clkout()
617 dev_info(dev, "It uses CLK_I as approximate rate"); in rsnd_adg_get_clkout()
626 * this means all clkout0/1/2/3 will be * same rate in rsnd_adg_get_clkout()
629 of_property_read_u32(np, "#clock-cells", &count); in rsnd_adg_get_clkout()
639 adg->clkout[CLKOUT] = clk; in rsnd_adg_get_clkout()
640 adg->clkout_size = 1; in rsnd_adg_get_clkout()
654 adg->clkout[i] = clk; in rsnd_adg_get_clkout()
656 adg->onecell.clks = adg->clkout; in rsnd_adg_get_clkout()
657 adg->onecell.clk_num = clkout_size; in rsnd_adg_get_clkout()
658 adg->clkout_size = clkout_size; in rsnd_adg_get_clkout()
660 &adg->onecell); in rsnd_adg_get_clkout()
664 adg->ckr = ckr; in rsnd_adg_get_clkout()
665 adg->brga = brga; in rsnd_adg_get_clkout()
666 adg->brgb = brgb; in rsnd_adg_get_clkout()
675 return -EIO; in rsnd_adg_get_clkout()
704 dbg_msg(dev, m, "%-18s : %pa : %ld\n", in rsnd_adg_clk_dbg_info()
708 adg->ckr, adg->brga, adg->brgb); in rsnd_adg_clk_dbg_info()
709 dbg_msg(dev, m, "BRGA (for 44100 base) = %d\n", adg->brg_rate[ADG_HZ_441]); in rsnd_adg_clk_dbg_info()
710 dbg_msg(dev, m, "BRGB (for 48000 base) = %d\n", adg->brg_rate[ADG_HZ_48]); in rsnd_adg_clk_dbg_info()
717 dbg_msg(dev, m, "%-18s : %pa : %ld\n", in rsnd_adg_clk_dbg_info()
732 return -ENOMEM; in rsnd_adg_probe()
734 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, in rsnd_adg_probe()
739 priv->adg = adg; in rsnd_adg_probe()
758 struct device_node *np = dev->of_node; in rsnd_adg_remove()