Lines Matching +full:0 +full:xc000
80 int chan = 0; in sc7180_lpass_alloc_dma_channel()
120 return 0; in sc7180_lpass_free_dma_channel()
137 for (i = 0; i < drvdata->num_clks; i++) in sc7180_lpass_init()
152 return 0; in sc7180_lpass_init()
160 return 0; in sc7180_lpass_exit()
175 return 0; in sc7180_lpass_dev_suspend()
183 .i2sctrl_reg_base = 0x1000,
184 .i2sctrl_reg_stride = 0x1000,
186 .irq_reg_base = 0x9000,
187 .irq_reg_stride = 0x1000,
189 .rdma_reg_base = 0xC000,
190 .rdma_reg_stride = 0x1000,
192 .hdmi_rdma_reg_base = 0x64000,
193 .hdmi_rdma_reg_stride = 0x1000,
196 .wrdma_reg_base = 0x18000,
197 .wrdma_reg_stride = 0x1000,
201 .loopback = REG_FIELD_ID(0x1000, 17, 17, 3, 0x1000),
202 .spken = REG_FIELD_ID(0x1000, 16, 16, 3, 0x1000),
203 .spkmode = REG_FIELD_ID(0x1000, 11, 15, 3, 0x1000),
204 .spkmono = REG_FIELD_ID(0x1000, 10, 10, 3, 0x1000),
205 .micen = REG_FIELD_ID(0x1000, 9, 9, 3, 0x1000),
206 .micmode = REG_FIELD_ID(0x1000, 4, 8, 3, 0x1000),
207 .micmono = REG_FIELD_ID(0x1000, 3, 3, 3, 0x1000),
208 .wssrc = REG_FIELD_ID(0x1000, 2, 2, 3, 0x1000),
209 .bitwidth = REG_FIELD_ID(0x1000, 0, 1, 3, 0x1000),
211 .rdma_dyncclk = REG_FIELD_ID(0xC000, 21, 21, 5, 0x1000),
212 .rdma_bursten = REG_FIELD_ID(0xC000, 20, 20, 5, 0x1000),
213 .rdma_wpscnt = REG_FIELD_ID(0xC000, 16, 19, 5, 0x1000),
214 .rdma_intf = REG_FIELD_ID(0xC000, 12, 15, 5, 0x1000),
215 .rdma_fifowm = REG_FIELD_ID(0xC000, 1, 5, 5, 0x1000),
216 .rdma_enable = REG_FIELD_ID(0xC000, 0, 0, 5, 0x1000),
218 .wrdma_dyncclk = REG_FIELD_ID(0x18000, 22, 22, 4, 0x1000),
219 .wrdma_bursten = REG_FIELD_ID(0x18000, 21, 21, 4, 0x1000),
220 .wrdma_wpscnt = REG_FIELD_ID(0x18000, 17, 20, 4, 0x1000),
221 .wrdma_intf = REG_FIELD_ID(0x18000, 12, 16, 4, 0x1000),
222 .wrdma_fifowm = REG_FIELD_ID(0x18000, 1, 5, 4, 0x1000),
223 .wrdma_enable = REG_FIELD_ID(0x18000, 0, 0, 4, 0x1000),
225 .hdmi_tx_ctl_addr = 0x1000,
226 .hdmi_legacy_addr = 0x1008,
227 .hdmi_vbit_addr = 0x610c0,
228 .hdmi_ch_lsb_addr = 0x61048,
229 .hdmi_ch_msb_addr = 0x6104c,
230 .ch_stride = 0x8,
231 .hdmi_parity_addr = 0x61034,
232 .hdmi_dmactl_addr = 0x61038,
233 .hdmi_dma_stride = 0x4,
234 .hdmi_DP_addr = 0x610c8,
235 .hdmi_sstream_addr = 0x6101c,
236 .hdmi_irq_reg_base = 0x63000,
239 .hdmi_rdma_dyncclk = REG_FIELD_ID(0x64000, 14, 14, 4, 0x1000),
240 .hdmi_rdma_bursten = REG_FIELD_ID(0x64000, 13, 13, 4, 0x1000),
241 .hdmi_rdma_burst8 = REG_FIELD_ID(0x64000, 15, 15, 4, 0x1000),
242 .hdmi_rdma_burst16 = REG_FIELD_ID(0x64000, 16, 16, 4, 0x1000),
243 .hdmi_rdma_dynburst = REG_FIELD_ID(0x64000, 18, 18, 4, 0x1000),
244 .hdmi_rdma_wpscnt = REG_FIELD_ID(0x64000, 10, 12, 4, 0x1000),
245 .hdmi_rdma_fifowm = REG_FIELD_ID(0x64000, 1, 5, 4, 0x1000),
246 .hdmi_rdma_enable = REG_FIELD_ID(0x64000, 0, 0, 4, 0x1000),
248 .sstream_en = REG_FIELD(0x6101c, 0, 0),
249 .dma_sel = REG_FIELD(0x6101c, 1, 2),
250 .auto_bbit_en = REG_FIELD(0x6101c, 3, 3),
251 .layout = REG_FIELD(0x6101c, 4, 4),
252 .layout_sp = REG_FIELD(0x6101c, 5, 8),
253 .set_sp_on_en = REG_FIELD(0x6101c, 10, 10),
254 .dp_audio = REG_FIELD(0x6101c, 11, 11),
255 .dp_staffing_en = REG_FIELD(0x6101c, 12, 12),
256 .dp_sp_b_hw_en = REG_FIELD(0x6101c, 13, 13),
258 .mute = REG_FIELD(0x610c8, 0, 0),
259 .as_sdp_cc = REG_FIELD(0x610c8, 1, 3),
260 .as_sdp_ct = REG_FIELD(0x610c8, 4, 7),
261 .aif_db4 = REG_FIELD(0x610c8, 8, 15),
262 .frequency = REG_FIELD(0x610c8, 16, 21),
263 .mst_index = REG_FIELD(0x610c8, 28, 29),
264 .dptx_index = REG_FIELD(0x610c8, 30, 31),
266 .soft_reset = REG_FIELD(0x1000, 31, 31),
267 .force_reset = REG_FIELD(0x1000, 30, 30),
269 .use_hw_chs = REG_FIELD(0x61038, 0, 0),
270 .use_hw_usr = REG_FIELD(0x61038, 1, 1),
271 .hw_chs_sel = REG_FIELD(0x61038, 2, 4),
272 .hw_usr_sel = REG_FIELD(0x61038, 5, 6),
274 .replace_vbit = REG_FIELD(0x610c0, 0, 0),
275 .vbit_stream = REG_FIELD(0x610c0, 1, 1),
277 .legacy_en = REG_FIELD(0x1008, 0, 0),
278 .calc_en = REG_FIELD(0x61034, 0, 0),
279 .lsb_bits = REG_FIELD(0x61048, 0, 31),
280 .msb_bits = REG_FIELD(0x6104c, 0, 31),