Lines Matching full:x1
26 #define BCK_INVERSE_MASK 0x1
27 #define BCK_INVERSE_MASK_SFT (0x1 << 3)
31 #define VUL12_ON_MASK 0x1
32 #define VUL12_ON_MASK_SFT (0x1 << 31)
34 #define MOD_DAI_ON_MASK 0x1
35 #define MOD_DAI_ON_MASK_SFT (0x1 << 30)
37 #define DAI_ON_MASK 0x1
38 #define DAI_ON_MASK_SFT (0x1 << 29)
40 #define DAI2_ON_MASK 0x1
41 #define DAI2_ON_MASK_SFT (0x1 << 28)
43 #define VUL6_ON_MASK 0x1
44 #define VUL6_ON_MASK_SFT (0x1 << 23)
46 #define VUL5_ON_MASK 0x1
47 #define VUL5_ON_MASK_SFT (0x1 << 22)
49 #define VUL4_ON_MASK 0x1
50 #define VUL4_ON_MASK_SFT (0x1 << 21)
52 #define VUL3_ON_MASK 0x1
53 #define VUL3_ON_MASK_SFT (0x1 << 20)
55 #define VUL2_ON_MASK 0x1
56 #define VUL2_ON_MASK_SFT (0x1 << 19)
58 #define VUL_ON_MASK 0x1
59 #define VUL_ON_MASK_SFT (0x1 << 18)
61 #define AWB2_ON_MASK 0x1
62 #define AWB2_ON_MASK_SFT (0x1 << 17)
64 #define AWB_ON_MASK 0x1
65 #define AWB_ON_MASK_SFT (0x1 << 16)
67 #define DL12_ON_MASK 0x1
68 #define DL12_ON_MASK_SFT (0x1 << 15)
70 #define DL9_ON_MASK 0x1
71 #define DL9_ON_MASK_SFT (0x1 << 12)
73 #define DL8_ON_MASK 0x1
74 #define DL8_ON_MASK_SFT (0x1 << 11)
76 #define DL7_ON_MASK 0x1
77 #define DL7_ON_MASK_SFT (0x1 << 10)
79 #define DL6_ON_MASK 0x1
80 #define DL6_ON_MASK_SFT (0x1 << 9)
82 #define DL5_ON_MASK 0x1
83 #define DL5_ON_MASK_SFT (0x1 << 8)
85 #define DL4_ON_MASK 0x1
86 #define DL4_ON_MASK_SFT (0x1 << 7)
88 #define DL3_ON_MASK 0x1
89 #define DL3_ON_MASK_SFT (0x1 << 6)
91 #define DL2_ON_MASK 0x1
92 #define DL2_ON_MASK_SFT (0x1 << 5)
94 #define DL1_ON_MASK 0x1
95 #define DL1_ON_MASK_SFT (0x1 << 4)
97 #define HDMI_OUT_ON_MASK 0x1
98 #define HDMI_OUT_ON_MASK_SFT (0x1 << 1)
100 #define AFE_ON_MASK 0x1
101 #define AFE_ON_MASK_SFT (0x1 << 0)
105 #define AFE_ON_RETM_MASK 0x1
106 #define AFE_ON_RETM_MASK_SFT (0x1 << 0)
110 #define BCK_NEG_EG_LATCH_MASK 0x1
111 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
113 #define BCK_INV_MASK 0x1
114 #define BCK_INV_MASK_SFT (0x1 << 29)
116 #define I2SIN_PAD_SEL_MASK 0x1
117 #define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
119 #define I2S_LOOPBACK_MASK 0x1
120 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
122 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
123 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
125 #define I2S1_HD_EN_MASK 0x1
126 #define I2S1_HD_EN_MASK_SFT (0x1 << 12)
131 #define INV_PAD_CTRL_MASK 0x1
132 #define INV_PAD_CTRL_MASK_SFT (0x1 << 7)
134 #define I2S_BYPSRC_MASK 0x1
135 #define I2S_BYPSRC_MASK_SFT (0x1 << 6)
137 #define INV_LRCK_MASK 0x1
138 #define INV_LRCK_MASK_SFT (0x1 << 5)
140 #define I2S_FMT_MASK 0x1
141 #define I2S_FMT_MASK_SFT (0x1 << 3)
143 #define I2S_SRC_MASK 0x1
144 #define I2S_SRC_MASK_SFT (0x1 << 2)
146 #define I2S_WLEN_MASK 0x1
147 #define I2S_WLEN_MASK_SFT (0x1 << 1)
149 #define I2S_EN_MASK 0x1
150 #define I2S_EN_MASK_SFT (0x1 << 0)
154 #define I2S2_LR_SWAP_MASK 0x1
155 #define I2S2_LR_SWAP_MASK_SFT (0x1 << 31)
157 #define I2S2_SEL_O19_O20_MASK 0x1
158 #define I2S2_SEL_O19_O20_MASK_SFT (0x1 << 18)
160 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
161 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
163 #define I2S2_SEL_O03_O04_MASK 0x1
164 #define I2S2_SEL_O03_O04_MASK_SFT (0x1 << 16)
166 #define I2S2_32BIT_EN_MASK 0x1
167 #define I2S2_32BIT_EN_MASK_SFT (0x1 << 13)
169 #define I2S2_HD_EN_MASK 0x1
170 #define I2S2_HD_EN_MASK_SFT (0x1 << 12)
175 #define INV_LRCK_MASK 0x1
176 #define INV_LRCK_MASK_SFT (0x1 << 5)
178 #define I2S2_FMT_MASK 0x1
179 #define I2S2_FMT_MASK_SFT (0x1 << 3)
181 #define I2S2_WLEN_MASK 0x1
182 #define I2S2_WLEN_MASK_SFT (0x1 << 1)
184 #define I2S2_EN_MASK 0x1
185 #define I2S2_EN_MASK_SFT (0x1 << 0)
189 #define I2S3_LR_SWAP_MASK 0x1
190 #define I2S3_LR_SWAP_MASK_SFT (0x1 << 31)
195 #define I2S3_BCK_INV_MASK 0x1
196 #define I2S3_BCK_INV_MASK_SFT (0x1 << 23)
198 #define I2S3_FPGA_BIT_TEST_MASK 0x1
199 #define I2S3_FPGA_BIT_TEST_MASK_SFT (0x1 << 22)
201 #define I2S3_FPGA_BIT_MASK 0x1
202 #define I2S3_FPGA_BIT_MASK_SFT (0x1 << 21)
204 #define I2S3_LOOPBACK_MASK 0x1
205 #define I2S3_LOOPBACK_MASK_SFT (0x1 << 20)
207 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
208 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
210 #define I2S3_HD_EN_MASK 0x1
211 #define I2S3_HD_EN_MASK_SFT (0x1 << 12)
216 #define I2S3_FMT_MASK 0x1
217 #define I2S3_FMT_MASK_SFT (0x1 << 3)
219 #define I2S3_WLEN_MASK 0x1
220 #define I2S3_WLEN_MASK_SFT (0x1 << 1)
222 #define I2S3_EN_MASK 0x1
223 #define I2S3_EN_MASK_SFT (0x1 << 0)
227 #define I2S4_LR_SWAP_MASK 0x1
228 #define I2S4_LR_SWAP_MASK_SFT (0x1 << 31)
230 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
231 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
233 #define I2S4_32BIT_EN_MASK 0x1
234 #define I2S4_32BIT_EN_MASK_SFT (0x1 << 13)
236 #define I2S4_HD_EN_MASK 0x1
237 #define I2S4_HD_EN_MASK_SFT (0x1 << 12)
242 #define INV_LRCK_MASK 0x1
243 #define INV_LRCK_MASK_SFT (0x1 << 5)
245 #define I2S4_FMT_MASK 0x1
246 #define I2S4_FMT_MASK_SFT (0x1 << 3)
248 #define I2S4_WLEN_MASK 0x1
249 #define I2S4_WLEN_MASK_SFT (0x1 << 1)
251 #define I2S4_EN_MASK 0x1
252 #define I2S4_EN_MASK_SFT (0x1 << 0)
256 #define I2S5_LR_SWAP_MASK 0x1
257 #define I2S5_LR_SWAP_MASK_SFT (0x1 << 31)
259 #define I2S_LOOPBACK_MASK 0x1
260 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
262 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
263 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
265 #define I2S5_32BIT_EN_MASK 0x1
266 #define I2S5_32BIT_EN_MASK_SFT (0x1 << 13)
268 #define I2S5_HD_EN_MASK 0x1
269 #define I2S5_HD_EN_MASK_SFT (0x1 << 12)
274 #define INV_LRCK_MASK 0x1
275 #define INV_LRCK_MASK_SFT (0x1 << 5)
277 #define I2S5_FMT_MASK 0x1
278 #define I2S5_FMT_MASK_SFT (0x1 << 3)
280 #define I2S5_WLEN_MASK 0x1
281 #define I2S5_WLEN_MASK_SFT (0x1 << 1)
283 #define I2S5_EN_MASK 0x1
284 #define I2S5_EN_MASK_SFT (0x1 << 0)
288 #define BCK_NEG_EG_LATCH_MASK 0x1
289 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
291 #define BCK_INV_MASK 0x1
292 #define BCK_INV_MASK_SFT (0x1 << 29)
294 #define I2SIN_PAD_SEL_MASK 0x1
295 #define I2SIN_PAD_SEL_MASK_SFT (0x1 << 28)
297 #define I2S_LOOPBACK_MASK 0x1
298 #define I2S_LOOPBACK_MASK_SFT (0x1 << 20)
300 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
301 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
306 #define INV_PAD_CTRL_MASK 0x1
307 #define INV_PAD_CTRL_MASK_SFT (0x1 << 7)
309 #define I2S_BYPSRC_MASK 0x1
310 #define I2S_BYPSRC_MASK_SFT (0x1 << 6)
312 #define INV_LRCK_MASK 0x1
313 #define INV_LRCK_MASK_SFT (0x1 << 5)
315 #define I2S_FMT_MASK 0x1
316 #define I2S_FMT_MASK_SFT (0x1 << 3)
318 #define I2S_SRC_MASK 0x1
319 #define I2S_SRC_MASK_SFT (0x1 << 2)
321 #define I2S_WLEN_MASK 0x1
322 #define I2S_WLEN_MASK_SFT (0x1 << 1)
324 #define I2S_EN_MASK 0x1
325 #define I2S_EN_MASK_SFT (0x1 << 0)
329 #define BCK_NEG_EG_LATCH_MASK 0x1
330 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
332 #define BCK_INV_MASK 0x1
333 #define BCK_INV_MASK_SFT (0x1 << 29)
335 #define I2S6_LOOPBACK_MASK 0x1
336 #define I2S6_LOOPBACK_MASK_SFT (0x1 << 20)
338 #define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
339 #define I2S6_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
341 #define I2S6_HD_EN_MASK 0x1
342 #define I2S6_HD_EN_MASK_SFT (0x1 << 12)
347 #define I2S6_BYPSRC_MASK 0x1
348 #define I2S6_BYPSRC_MASK_SFT (0x1 << 6)
350 #define INV_LRCK_MASK 0x1
351 #define INV_LRCK_MASK_SFT (0x1 << 5)
353 #define I2S6_FMT_MASK 0x1
354 #define I2S6_FMT_MASK_SFT (0x1 << 3)
356 #define I2S6_SRC_MASK 0x1
357 #define I2S6_SRC_MASK_SFT (0x1 << 2)
359 #define I2S6_WLEN_MASK 0x1
360 #define I2S6_WLEN_MASK_SFT (0x1 << 1)
362 #define I2S6_EN_MASK 0x1
363 #define I2S6_EN_MASK_SFT (0x1 << 0)
367 #define I2S7_LR_SWAP_MASK 0x1
368 #define I2S7_LR_SWAP_MASK_SFT (0x1 << 31)
370 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
371 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
373 #define I2S7_32BIT_EN_MASK 0x1
374 #define I2S7_32BIT_EN_MASK_SFT (0x1 << 13)
376 #define I2S7_HD_EN_MASK 0x1
377 #define I2S7_HD_EN_MASK_SFT (0x1 << 12)
382 #define INV_LRCK_MASK 0x1
383 #define INV_LRCK_MASK_SFT (0x1 << 5)
385 #define I2S7_FMT_MASK 0x1
386 #define I2S7_FMT_MASK_SFT (0x1 << 3)
388 #define I2S7_WLEN_MASK 0x1
389 #define I2S7_WLEN_MASK_SFT (0x1 << 1)
391 #define I2S7_EN_MASK 0x1
392 #define I2S7_EN_MASK_SFT (0x1 << 0)
396 #define BCK_NEG_EG_LATCH_MASK 0x1
397 #define BCK_NEG_EG_LATCH_MASK_SFT (0x1 << 30)
399 #define BCK_INV_MASK 0x1
400 #define BCK_INV_MASK_SFT (0x1 << 29)
402 #define I2S8_LOOPBACK_MASK 0x1
403 #define I2S8_LOOPBACK_MASK_SFT (0x1 << 20)
405 #define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
406 #define I2S8_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
408 #define I2S8_HD_EN_MASK 0x1
409 #define I2S8_HD_EN_MASK_SFT (0x1 << 12)
414 #define I2S8_BYPSRC_MASK 0x1
415 #define I2S8_BYPSRC_MASK_SFT (0x1 << 6)
417 #define INV_LRCK_MASK 0x1
418 #define INV_LRCK_MASK_SFT (0x1 << 5)
420 #define I2S8_FMT_MASK 0x1
421 #define I2S8_FMT_MASK_SFT (0x1 << 3)
423 #define I2S8_SRC_MASK 0x1
424 #define I2S8_SRC_MASK_SFT (0x1 << 2)
426 #define I2S8_WLEN_MASK 0x1
427 #define I2S8_WLEN_MASK_SFT (0x1 << 1)
429 #define I2S8_EN_MASK 0x1
430 #define I2S8_EN_MASK_SFT (0x1 << 0)
434 #define I2S9_LR_SWAP_MASK 0x1
435 #define I2S9_LR_SWAP_MASK_SFT (0x1 << 31)
437 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK 0x1
438 #define I2S_ONOFF_NOT_RESET_CK_ENABLE_MASK_SFT (0x1 << 17)
440 #define I2S9_32BIT_EN_MASK 0x1
441 #define I2S9_32BIT_EN_MASK_SFT (0x1 << 13)
443 #define I2S9_HD_EN_MASK 0x1
444 #define I2S9_HD_EN_MASK_SFT (0x1 << 12)
449 #define INV_LRCK_MASK 0x1
450 #define INV_LRCK_MASK_SFT (0x1 << 5)
452 #define I2S9_FMT_MASK 0x1
453 #define I2S9_FMT_MASK_SFT (0x1 << 3)
455 #define I2S9_WLEN_MASK 0x1
456 #define I2S9_WLEN_MASK_SFT (0x1 << 1)
458 #define I2S9_EN_MASK 0x1
459 #define I2S9_EN_MASK_SFT (0x1 << 0)
463 #define CHSET_O16BIT_MASK 0x1
464 #define CHSET_O16BIT_MASK_SFT (0x1 << 19)
466 #define CHSET_CLR_IIR_HISTORY_MASK 0x1
467 #define CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)
469 #define CHSET_IS_MONO_MASK 0x1
470 #define CHSET_IS_MONO_MASK_SFT (0x1 << 16)
472 #define CHSET_IIR_EN_MASK 0x1
473 #define CHSET_IIR_EN_MASK_SFT (0x1 << 11)
478 #define CHSET_STR_CLR_MASK 0x1
479 #define CHSET_STR_CLR_MASK_SFT (0x1 << 5)
481 #define CHSET_ON_MASK 0x1
482 #define CHSET_ON_MASK_SFT (0x1 << 2)
484 #define COEFF_SRAM_CTRL_MASK 0x1
485 #define COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
487 #define ASM_ON_MASK 0x1
488 #define ASM_ON_MASK_SFT (0x1 << 0)
498 #define GAIN1_ON_MASK 0x1
499 #define GAIN1_ON_MASK_SFT (0x1 << 0)
514 #define GAIN2_ON_MASK 0x1
515 #define GAIN2_ON_MASK_SFT (0x1 << 0)
534 #define PCM_FIX_VALUE_SEL_MASK 0x1
535 #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
537 #define PCM_BUFFER_LOOPBACK_MASK 0x1
538 #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
540 #define PCM_PARALLEL_LOOPBACK_MASK 0x1
541 #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
543 #define PCM_SERIAL_LOOPBACK_MASK 0x1
544 #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
546 #define PCM_DAI_PCM_LOOPBACK_MASK 0x1
547 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
549 #define PCM_I2S_PCM_LOOPBACK_MASK 0x1
550 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
552 #define PCM_SYNC_DELSEL_MASK 0x1
553 #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
555 #define PCM_TX_LR_SWAP_MASK 0x1
556 #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
558 #define PCM_SYNC_OUT_INV_MASK 0x1
559 #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
561 #define PCM_BCLK_OUT_INV_MASK 0x1
562 #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
564 #define PCM_SYNC_IN_INV_MASK 0x1
565 #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
567 #define PCM_BCLK_IN_INV_MASK 0x1
568 #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
570 #define PCM_TX_LCH_RPT_MASK 0x1
571 #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
573 #define PCM_VBT_16K_MODE_MASK 0x1
574 #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
576 #define PCM_EXT_MODEM_MASK 0x1
577 #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
579 #define PCM_24BIT_MASK 0x1
580 #define PCM_24BIT_MASK_SFT (0x1 << 16)
588 #define PCM_SYNC_TYPE_MASK 0x1
589 #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
591 #define PCM_BT_MODE_MASK 0x1
592 #define PCM_BT_MODE_MASK_SFT (0x1 << 7)
594 #define PCM_BYP_ASRC_MASK 0x1
595 #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
597 #define PCM_SLAVE_MASK 0x1
598 #define PCM_SLAVE_MASK_SFT (0x1 << 5)
606 #define PCM_EN_MASK 0x1
607 #define PCM_EN_MASK_SFT (0x1 << 0)
611 #define PCM1_TX_FIFO_OV_MASK 0x1
612 #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
614 #define PCM1_RX_FIFO_OV_MASK 0x1
615 #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
617 #define PCM2_TX_FIFO_OV_MASK 0x1
618 #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
620 #define PCM2_RX_FIFO_OV_MASK 0x1
621 #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
623 #define PCM1_SYNC_GLITCH_MASK 0x1
624 #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
626 #define PCM2_SYNC_GLITCH_MASK 0x1
627 #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
629 #define TX3_RCH_DBG_MODE_MASK 0x1
630 #define TX3_RCH_DBG_MODE_MASK_SFT (0x1 << 17)
632 #define PCM1_PCM2_LOOPBACK_MASK 0x1
633 #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 16)
649 #define PCM2_FIX_VALUE_SEL_MASK 0x1
650 #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
652 #define PCM2_BUFFER_LOOPBACK_MASK 0x1
653 #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
655 #define PCM2_PARALLEL_LOOPBACK_MASK 0x1
656 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
658 #define PCM2_SERIAL_LOOPBACK_MASK 0x1
659 #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
661 #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
662 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
664 #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
665 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
667 #define PCM2_SYNC_DELSEL_MASK 0x1
668 #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
670 #define PCM2_TX_LR_SWAP_MASK 0x1
671 #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
673 #define PCM2_SYNC_IN_INV_MASK 0x1
674 #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
676 #define PCM2_BCLK_IN_INV_MASK 0x1
677 #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
679 #define PCM2_TX_LCH_RPT_MASK 0x1
680 #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
682 #define PCM2_VBT_16K_MODE_MASK 0x1
683 #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
688 #define PCM2_TX2_BT_MODE_MASK 0x1
689 #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
691 #define PCM2_BT_MODE_MASK 0x1
692 #define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
694 #define PCM2_AFIFO_MASK 0x1
695 #define PCM2_AFIFO_MASK_SFT (0x1 << 6)
697 #define PCM2_WLEN_MASK 0x1
698 #define PCM2_WLEN_MASK_SFT (0x1 << 5)
706 #define PCM2_EN_MASK 0x1
707 #define PCM2_EN_MASK_SFT (0x1 << 0)
711 #define MTKAIF_RXIF_CLKINV_ADC_MASK 0x1
712 #define MTKAIF_RXIF_CLKINV_ADC_MASK_SFT (0x1 << 31)
714 #define MTKAIF_RXIF_BYPASS_SRC_MASK 0x1
715 #define MTKAIF_RXIF_BYPASS_SRC_MASK_SFT (0x1 << 17)
717 #define MTKAIF_RXIF_PROTOCOL2_MASK 0x1
718 #define MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 16)
720 #define MTKAIF_TXIF_BYPASS_SRC_MASK 0x1
721 #define MTKAIF_TXIF_BYPASS_SRC_MASK_SFT (0x1 << 5)
723 #define MTKAIF_TXIF_PROTOCOL2_MASK 0x1
724 #define MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
726 #define MTKAIF_TXIF_8TO5_MASK 0x1
727 #define MTKAIF_TXIF_8TO5_MASK_SFT (0x1 << 2)
729 #define MTKAIF_RXIF_8TO5_MASK 0x1
730 #define MTKAIF_RXIF_8TO5_MASK_SFT (0x1 << 1)
732 #define MTKAIF_IF_LOOPBACK1_MASK 0x1
733 #define MTKAIF_IF_LOOPBACK1_MASK_SFT (0x1 << 0)
737 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
738 #define MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 16)
743 #define MTKAIF_RXIF_DELAY_DATA_MASK 0x1
744 #define MTKAIF_RXIF_DELAY_DATA_MASK_SFT (0x1 << 8)
754 #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1
755 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)
757 #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1
758 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)
766 #define DL_DISABLE_HW_CG_CTL_MASK 0x1
767 #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
769 #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1
770 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)
772 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1
773 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)
775 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
776 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
778 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
779 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
787 #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1
788 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
790 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1
791 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
793 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1
794 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
796 #define DL_2_IIR_ON_CTL_PRE_MASK 0x1
797 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)
799 #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1
800 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
802 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
803 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
810 #define DL_2_GAIN_MODE_CTL_MASK 0x1
811 #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)
815 #define ULCF_CFG_EN_CTL_MASK 0x1
816 #define ULCF_CFG_EN_CTL_MASK_SFT (0x1 << 31)
824 #define UL_MODE_3P25M_CH2_CTL_MASK 0x1
825 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
827 #define UL_MODE_3P25M_CH1_CTL_MASK 0x1
828 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
833 #define UL_AP_DMIC_ON_MASK 0x1
834 #define UL_AP_DMIC_ON_MASK_SFT (0x1 << 16)
839 #define UL_DISABLE_HW_CG_CTL_MASK 0x1
840 #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
842 #define UL_IIR_ON_TMP_CTL_MASK 0x1
843 #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
848 #define DIGMIC_4P33M_SEL_MASK 0x1
849 #define DIGMIC_4P33M_SEL_MASK_SFT (0x1 << 6)
851 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
852 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
854 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
855 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
857 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
858 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
860 #define UL_SRC_ON_TMP_CTL_MASK 0x1
861 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
865 #define C_DAC_EN_CTL_MASK 0x1
866 #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
868 #define C_MUTE_SW_CTL_MASK 0x1
869 #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
871 #define ASDM_SRC_SEL_CTL_MASK 0x1
872 #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)
900 #define C_EXT_ADC_CTL_MASK 0x1
901 #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)
905 #define AFE_ADDA_UL_LR_SWAP_MASK 0x1
906 #define AFE_ADDA_UL_LR_SWAP_MASK_SFT (0x1 << 31)
908 #define AFE_ADDA_CKDIV_RST_MASK 0x1
909 #define AFE_ADDA_CKDIV_RST_MASK_SFT (0x1 << 30)
911 #define AFE_ADDA_FIFO_AUTO_RST_MASK 0x1
912 #define AFE_ADDA_FIFO_AUTO_RST_MASK_SFT (0x1 << 29)
917 #define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
918 #define AFE_ADDA_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 20)
920 #define AFE_ADDA6_UL_LR_SWAP_MASK 0x1
921 #define AFE_ADDA6_UL_LR_SWAP_MASK_SFT (0x1 << 15)
923 #define AFE_ADDA6_CKDIV_RST_MASK 0x1
924 #define AFE_ADDA6_CKDIV_RST_MASK_SFT (0x1 << 14)
926 #define AFE_ADDA6_FIFO_AUTO_RST_MASK 0x1
927 #define AFE_ADDA6_FIFO_AUTO_RST_MASK_SFT (0x1 << 13)
932 #define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK 0x1
933 #define AFE_ADDA6_UL_FIFO_DIGMIC_WDATA_TESTEN_MASK_SFT (0x1 << 4)
935 #define ADDA_AFE_ON_MASK 0x1
936 #define ADDA_AFE_ON_MASK_SFT (0x1 << 0)
940 #define R_RDY_MASK 0x1
941 #define R_RDY_MASK_SFT (0x1 << 30)
943 #define W_RDY_MASK 0x1
944 #define W_RDY_MASK_SFT (0x1 << 29)
946 #define R_W_EN_MASK 0x1
947 #define R_W_EN_MASK_SFT (0x1 << 25)
949 #define R_W_SEL_MASK 0x1
950 #define R_W_SEL_MASK_SFT (0x1 << 24)
952 #define SEL_CH2_MASK 0x1
953 #define SEL_CH2_MASK_SFT (0x1 << 23)
968 #define STF_BYPASS_MODE_MASK 0x1
969 #define STF_BYPASS_MODE_MASK_SFT (0x1 << 31)
971 #define STF_BYPASS_MODE_O28_O29_MASK 0x1
972 #define STF_BYPASS_MODE_O28_O29_MASK_SFT (0x1 << 30)
974 #define STF_BYPASS_MODE_I2S4_MASK 0x1
975 #define STF_BYPASS_MODE_I2S4_MASK_SFT (0x1 << 29)
977 #define STF_BYPASS_MODE_I2S5_MASK 0x1
978 #define STF_BYPASS_MODE_I2S5_MASK_SFT (0x1 << 28)
980 #define STF_BYPASS_MODE_DL3_MASK 0x1
981 #define STF_BYPASS_MODE_DL3_MASK_SFT (0x1 << 27)
983 #define STF_BYPASS_MODE_I2S7_MASK 0x1
984 #define STF_BYPASS_MODE_I2S7_MASK_SFT (0x1 << 26)
986 #define STF_BYPASS_MODE_I2S9_MASK 0x1
987 #define STF_BYPASS_MODE_I2S9_MASK_SFT (0x1 << 25)
989 #define STF_O19O20_OUT_EN_SEL_MASK 0x1
990 #define STF_O19O20_OUT_EN_SEL_MASK_SFT (0x1 << 13)
992 #define STF_SOURCE_FROM_O19O20_MASK 0x1
993 #define STF_SOURCE_FROM_O19O20_MASK_SFT (0x1 << 12)
995 #define SIDE_TONE_ON_MASK 0x1
996 #define SIDE_TONE_ON_MASK_SFT (0x1 << 8)
1011 #define USE_3RD_SDM_MASK 0x1
1012 #define USE_3RD_SDM_MASK_SFT (0x1 << 28)
1017 #define DL_FIFO_SWAP_MASK 0x1
1018 #define DL_FIFO_SWAP_MASK_SFT (0x1 << 20)
1020 #define C_AUDSDM1ORDSELECT_CTL_MASK 0x1
1021 #define C_AUDSDM1ORDSELECT_CTL_MASK_SFT (0x1 << 19)
1023 #define C_SDM7BITSEL_CTL_MASK 0x1
1024 #define C_SDM7BITSEL_CTL_MASK_SFT (0x1 << 18)
1026 #define GAIN_AT_SDM_RST_PRE_CTL_MASK 0x1
1027 #define GAIN_AT_SDM_RST_PRE_CTL_MASK_SFT (0x1 << 15)
1029 #define DL_DCM_AUTO_IDLE_EN_MASK 0x1
1030 #define DL_DCM_AUTO_IDLE_EN_MASK_SFT (0x1 << 14)
1032 #define AFE_DL_SRC_DCM_EN_MASK 0x1
1033 #define AFE_DL_SRC_DCM_EN_MASK_SFT (0x1 << 13)
1035 #define AFE_DL_POST_SRC_DCM_EN_MASK 0x1
1036 #define AFE_DL_POST_SRC_DCM_EN_MASK_SFT (0x1 << 12)
1038 #define AUD_SDM_MONO_MASK 0x1
1039 #define AUD_SDM_MONO_MASK_SFT (0x1 << 9)
1041 #define AUD_DC_COMP_EN_MASK 0x1
1042 #define AUD_DC_COMP_EN_MASK_SFT (0x1 << 8)
1049 #define DAC_EN_MASK 0x1
1050 #define DAC_EN_MASK_SFT (0x1 << 26)
1052 #define MUTE_SW_CH2_MASK 0x1
1053 #define MUTE_SW_CH2_MASK_SFT (0x1 << 25)
1055 #define MUTE_SW_CH1_MASK 0x1
1056 #define MUTE_SW_CH1_MASK_SFT (0x1 << 24)
1083 #define AFE_24M_ON_MASK 0x1
1084 #define AFE_24M_ON_MASK_SFT (0x1 << 1)
1086 #define AFE_22M_ON_MASK 0x1
1087 #define AFE_22M_ON_MASK_SFT (0x1 << 0)
1097 #define DL_NLE_FIFO_RDACTIVE_MASK 0x1
1098 #define DL_NLE_FIFO_RDACTIVE_MASK_SFT (0x1 << 3)
1100 #define DL_NLE_FIFO_STARTRD_MASK 0x1
1101 #define DL_NLE_FIFO_STARTRD_MASK_SFT (0x1 << 2)
1103 #define DL_NLE_FIFO_RD_EMPTY_MASK 0x1
1104 #define DL_NLE_FIFO_RD_EMPTY_MASK_SFT (0x1 << 1)
1106 #define DL_NLE_FIFO_WR_FULL_MASK 0x1
1107 #define DL_NLE_FIFO_WR_FULL_MASK_SFT (0x1 << 0)
1120 #define DL1_SW_CLEAR_BUF_EMPTY_MASK 0x1
1121 #define DL1_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1126 #define DL1_MONO_MASK 0x1
1127 #define DL1_MONO_MASK_SFT (0x1 << 8)
1129 #define DL1_NORMAL_MODE_MASK 0x1
1130 #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 5)
1132 #define DL1_HALIGN_MASK 0x1
1133 #define DL1_HALIGN_MASK_SFT (0x1 << 4)
1149 #define DL2_SW_CLEAR_BUF_EMPTY_MASK 0x1
1150 #define DL2_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1155 #define DL2_MONO_MASK 0x1
1156 #define DL2_MONO_MASK_SFT (0x1 << 8)
1158 #define DL2_NORMAL_MODE_MASK 0x1
1159 #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1161 #define DL2_HALIGN_MASK 0x1
1162 #define DL2_HALIGN_MASK_SFT (0x1 << 4)
1178 #define DL3_SW_CLEAR_BUF_EMPTY_MASK 0x1
1179 #define DL3_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1184 #define DL3_MONO_MASK 0x1
1185 #define DL3_MONO_MASK_SFT (0x1 << 8)
1187 #define DL3_NORMAL_MODE_MASK 0x1
1188 #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 5)
1190 #define DL3_HALIGN_MASK 0x1
1191 #define DL3_HALIGN_MASK_SFT (0x1 << 4)
1207 #define DL4_SW_CLEAR_BUF_EMPTY_MASK 0x1
1208 #define DL4_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1213 #define DL4_MONO_MASK 0x1
1214 #define DL4_MONO_MASK_SFT (0x1 << 8)
1216 #define DL4_NORMAL_MODE_MASK 0x1
1217 #define DL4_NORMAL_MODE_MASK_SFT (0x1 << 5)
1219 #define DL4_HALIGN_MASK 0x1
1220 #define DL4_HALIGN_MASK_SFT (0x1 << 4)
1236 #define DL5_SW_CLEAR_BUF_EMPTY_MASK 0x1
1237 #define DL5_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1242 #define DL5_MONO_MASK 0x1
1243 #define DL5_MONO_MASK_SFT (0x1 << 8)
1245 #define DL5_NORMAL_MODE_MASK 0x1
1246 #define DL5_NORMAL_MODE_MASK_SFT (0x1 << 5)
1248 #define DL5_HALIGN_MASK 0x1
1249 #define DL5_HALIGN_MASK_SFT (0x1 << 4)
1265 #define DL6_SW_CLEAR_BUF_EMPTY_MASK 0x1
1266 #define DL6_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1271 #define DL6_MONO_MASK 0x1
1272 #define DL6_MONO_MASK_SFT (0x1 << 8)
1274 #define DL6_NORMAL_MODE_MASK 0x1
1275 #define DL6_NORMAL_MODE_MASK_SFT (0x1 << 5)
1277 #define DL6_HALIGN_MASK 0x1
1278 #define DL6_HALIGN_MASK_SFT (0x1 << 4)
1294 #define DL7_SW_CLEAR_BUF_EMPTY_MASK 0x1
1295 #define DL7_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1300 #define DL7_MONO_MASK 0x1
1301 #define DL7_MONO_MASK_SFT (0x1 << 8)
1303 #define DL7_NORMAL_MODE_MASK 0x1
1304 #define DL7_NORMAL_MODE_MASK_SFT (0x1 << 5)
1306 #define DL7_HALIGN_MASK 0x1
1307 #define DL7_HALIGN_MASK_SFT (0x1 << 4)
1323 #define DL8_SW_CLEAR_BUF_EMPTY_MASK 0x1
1324 #define DL8_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1329 #define DL8_MONO_MASK 0x1
1330 #define DL8_MONO_MASK_SFT (0x1 << 8)
1332 #define DL8_NORMAL_MODE_MASK 0x1
1333 #define DL8_NORMAL_MODE_MASK_SFT (0x1 << 5)
1335 #define DL8_HALIGN_MASK 0x1
1336 #define DL8_HALIGN_MASK_SFT (0x1 << 4)
1352 #define DL9_SW_CLEAR_BUF_EMPTY_MASK 0x1
1353 #define DL9_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1358 #define DL9_MONO_MASK 0x1
1359 #define DL9_MONO_MASK_SFT (0x1 << 8)
1361 #define DL9_NORMAL_MODE_MASK 0x1
1362 #define DL9_NORMAL_MODE_MASK_SFT (0x1 << 5)
1364 #define DL9_HALIGN_MASK 0x1
1365 #define DL9_HALIGN_MASK_SFT (0x1 << 4)
1381 #define DL12_SW_CLEAR_BUF_EMPTY_MASK 0x1
1382 #define DL12_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1387 #define DL12_4CH_EN_MASK 0x1
1388 #define DL12_4CH_EN_MASK_SFT (0x1 << 11)
1390 #define DL12_MONO_MASK 0x1
1391 #define DL12_MONO_MASK_SFT (0x1 << 8)
1393 #define DL12_NORMAL_MODE_MASK 0x1
1394 #define DL12_NORMAL_MODE_MASK_SFT (0x1 << 5)
1396 #define DL12_HALIGN_MASK 0x1
1397 #define DL12_HALIGN_MASK_SFT (0x1 << 4)
1407 #define AWB_SW_CLEAR_BUF_FULL_MASK 0x1
1408 #define AWB_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1410 #define AWB_R_MONO_MASK 0x1
1411 #define AWB_R_MONO_MASK_SFT (0x1 << 9)
1413 #define AWB_MONO_MASK 0x1
1414 #define AWB_MONO_MASK_SFT (0x1 << 8)
1416 #define AWB_WR_SIGN_MASK 0x1
1417 #define AWB_WR_SIGN_MASK_SFT (0x1 << 6)
1419 #define AWB_NORMAL_MODE_MASK 0x1
1420 #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 5)
1422 #define AWB_HALIGN_MASK 0x1
1423 #define AWB_HALIGN_MASK_SFT (0x1 << 4)
1433 #define AWB2_SW_CLEAR_BUF_FULL_MASK 0x1
1434 #define AWB2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1436 #define AWB2_R_MONO_MASK 0x1
1437 #define AWB2_R_MONO_MASK_SFT (0x1 << 9)
1439 #define AWB2_MONO_MASK 0x1
1440 #define AWB2_MONO_MASK_SFT (0x1 << 8)
1442 #define AWB2_WR_SIGN_MASK 0x1
1443 #define AWB2_WR_SIGN_MASK_SFT (0x1 << 6)
1445 #define AWB2_NORMAL_MODE_MASK 0x1
1446 #define AWB2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1448 #define AWB2_HALIGN_MASK 0x1
1449 #define AWB2_HALIGN_MASK_SFT (0x1 << 4)
1459 #define VUL_SW_CLEAR_BUF_FULL_MASK 0x1
1460 #define VUL_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1462 #define VUL_R_MONO_MASK 0x1
1463 #define VUL_R_MONO_MASK_SFT (0x1 << 9)
1465 #define VUL_MONO_MASK 0x1
1466 #define VUL_MONO_MASK_SFT (0x1 << 8)
1468 #define VUL_WR_SIGN_MASK 0x1
1469 #define VUL_WR_SIGN_MASK_SFT (0x1 << 6)
1471 #define VUL_NORMAL_MODE_MASK 0x1
1472 #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 5)
1474 #define VUL_HALIGN_MASK 0x1
1475 #define VUL_HALIGN_MASK_SFT (0x1 << 4)
1485 #define VUL12_SW_CLEAR_BUF_FULL_MASK 0x1
1486 #define VUL12_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1488 #define VUL12_4CH_EN_MASK 0x1
1489 #define VUL12_4CH_EN_MASK_SFT (0x1 << 11)
1491 #define VUL12_R_MONO_MASK 0x1
1492 #define VUL12_R_MONO_MASK_SFT (0x1 << 9)
1494 #define VUL12_MONO_MASK 0x1
1495 #define VUL12_MONO_MASK_SFT (0x1 << 8)
1497 #define VUL12_WR_SIGN_MASK 0x1
1498 #define VUL12_WR_SIGN_MASK_SFT (0x1 << 6)
1500 #define VUL12_NORMAL_MODE_MASK 0x1
1501 #define VUL12_NORMAL_MODE_MASK_SFT (0x1 << 5)
1503 #define VUL12_HALIGN_MASK 0x1
1504 #define VUL12_HALIGN_MASK_SFT (0x1 << 4)
1514 #define VUL2_SW_CLEAR_BUF_FULL_MASK 0x1
1515 #define VUL2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1517 #define VUL2_R_MONO_MASK 0x1
1518 #define VUL2_R_MONO_MASK_SFT (0x1 << 9)
1520 #define VUL2_MONO_MASK 0x1
1521 #define VUL2_MONO_MASK_SFT (0x1 << 8)
1523 #define VUL2_WR_SIGN_MASK 0x1
1524 #define VUL2_WR_SIGN_MASK_SFT (0x1 << 6)
1526 #define VUL2_NORMAL_MODE_MASK 0x1
1527 #define VUL2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1529 #define VUL2_HALIGN_MASK 0x1
1530 #define VUL2_HALIGN_MASK_SFT (0x1 << 4)
1540 #define VUL3_SW_CLEAR_BUF_FULL_MASK 0x1
1541 #define VUL3_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1543 #define VUL3_R_MONO_MASK 0x1
1544 #define VUL3_R_MONO_MASK_SFT (0x1 << 9)
1546 #define VUL3_MONO_MASK 0x1
1547 #define VUL3_MONO_MASK_SFT (0x1 << 8)
1549 #define VUL3_WR_SIGN_MASK 0x1
1550 #define VUL3_WR_SIGN_MASK_SFT (0x1 << 6)
1552 #define VUL3_NORMAL_MODE_MASK 0x1
1553 #define VUL3_NORMAL_MODE_MASK_SFT (0x1 << 5)
1555 #define VUL3_HALIGN_MASK 0x1
1556 #define VUL3_HALIGN_MASK_SFT (0x1 << 4)
1566 #define VUL4_SW_CLEAR_BUF_FULL_MASK 0x1
1567 #define VUL4_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1569 #define VUL4_R_MONO_MASK 0x1
1570 #define VUL4_R_MONO_MASK_SFT (0x1 << 9)
1572 #define VUL4_MONO_MASK 0x1
1573 #define VUL4_MONO_MASK_SFT (0x1 << 8)
1575 #define VUL4_WR_SIGN_MASK 0x1
1576 #define VUL4_WR_SIGN_MASK_SFT (0x1 << 6)
1578 #define VUL4_NORMAL_MODE_MASK 0x1
1579 #define VUL4_NORMAL_MODE_MASK_SFT (0x1 << 5)
1581 #define VUL4_HALIGN_MASK 0x1
1582 #define VUL4_HALIGN_MASK_SFT (0x1 << 4)
1592 #define VUL5_SW_CLEAR_BUF_FULL_MASK 0x1
1593 #define VUL5_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1595 #define VUL5_R_MONO_MASK 0x1
1596 #define VUL5_R_MONO_MASK_SFT (0x1 << 9)
1598 #define VUL5_MONO_MASK 0x1
1599 #define VUL5_MONO_MASK_SFT (0x1 << 8)
1601 #define VUL5_WR_SIGN_MASK 0x1
1602 #define VUL5_WR_SIGN_MASK_SFT (0x1 << 6)
1604 #define VUL5_NORMAL_MODE_MASK 0x1
1605 #define VUL5_NORMAL_MODE_MASK_SFT (0x1 << 5)
1607 #define VUL5_HALIGN_MASK 0x1
1608 #define VUL5_HALIGN_MASK_SFT (0x1 << 4)
1618 #define VUL6_SW_CLEAR_BUF_FULL_MASK 0x1
1619 #define VUL6_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1621 #define VUL6_R_MONO_MASK 0x1
1622 #define VUL6_R_MONO_MASK_SFT (0x1 << 9)
1624 #define VUL6_MONO_MASK 0x1
1625 #define VUL6_MONO_MASK_SFT (0x1 << 8)
1627 #define VUL6_WR_SIGN_MASK 0x1
1628 #define VUL6_WR_SIGN_MASK_SFT (0x1 << 6)
1630 #define VUL6_NORMAL_MODE_MASK 0x1
1631 #define VUL6_NORMAL_MODE_MASK_SFT (0x1 << 5)
1633 #define VUL6_HALIGN_MASK 0x1
1634 #define VUL6_HALIGN_MASK_SFT (0x1 << 4)
1644 #define DAI_SW_CLEAR_BUF_FULL_MASK 0x1
1645 #define DAI_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1647 #define DAI_DUPLICATE_WR_MASK 0x1
1648 #define DAI_DUPLICATE_WR_MASK_SFT (0x1 << 10)
1650 #define DAI_MONO_MASK 0x1
1651 #define DAI_MONO_MASK_SFT (0x1 << 8)
1653 #define DAI_WR_SIGN_MASK 0x1
1654 #define DAI_WR_SIGN_MASK_SFT (0x1 << 6)
1656 #define DAI_NORMAL_MODE_MASK 0x1
1657 #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 5)
1659 #define DAI_HALIGN_MASK 0x1
1660 #define DAI_HALIGN_MASK_SFT (0x1 << 4)
1670 #define MOD_DAI_SW_CLEAR_BUF_FULL_MASK 0x1
1671 #define MOD_DAI_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1673 #define MOD_DAI_DUPLICATE_WR_MASK 0x1
1674 #define MOD_DAI_DUPLICATE_WR_MASK_SFT (0x1 << 10)
1676 #define MOD_DAI_MONO_MASK 0x1
1677 #define MOD_DAI_MONO_MASK_SFT (0x1 << 8)
1679 #define MOD_DAI_WR_SIGN_MASK 0x1
1680 #define MOD_DAI_WR_SIGN_MASK_SFT (0x1 << 6)
1682 #define MOD_DAI_NORMAL_MODE_MASK 0x1
1683 #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 5)
1685 #define MOD_DAI_HALIGN_MASK 0x1
1686 #define MOD_DAI_HALIGN_MASK_SFT (0x1 << 4)
1696 #define DAI2_SW_CLEAR_BUF_FULL_MASK 0x1
1697 #define DAI2_SW_CLEAR_BUF_FULL_MASK_SFT (0x1 << 15)
1699 #define DAI2_DUPLICATE_WR_MASK 0x1
1700 #define DAI2_DUPLICATE_WR_MASK_SFT (0x1 << 10)
1702 #define DAI2_MONO_MASK 0x1
1703 #define DAI2_MONO_MASK_SFT (0x1 << 8)
1705 #define DAI2_WR_SIGN_MASK 0x1
1706 #define DAI2_WR_SIGN_MASK_SFT (0x1 << 6)
1708 #define DAI2_NORMAL_MODE_MASK 0x1
1709 #define DAI2_NORMAL_MODE_MASK_SFT (0x1 << 5)
1711 #define DAI2_HALIGN_MASK 0x1
1712 #define DAI2_HALIGN_MASK_SFT (0x1 << 4)
1719 #define CPU_COMPACT_MODE_MASK 0x1
1720 #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 2)
1722 #define CPU_HD_ALIGN_MASK 0x1
1723 #define CPU_HD_ALIGN_MASK_SFT (0x1 << 1)
1725 #define SYSRAM_SIGN_MASK 0x1
1726 #define SYSRAM_SIGN_MASK_SFT (0x1 << 0)
1739 #define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK 0x1
1740 #define HDMI_OUT_SW_CLEAR_BUF_EMPTY_MASK_SFT (0x1 << 15)
1745 #define HDMI_OUT_NORMAL_MODE_MASK 0x1
1746 #define HDMI_OUT_NORMAL_MODE_MASK_SFT (0x1 << 5)
1748 #define HDMI_OUT_HALIGN_MASK 0x1
1749 #define HDMI_OUT_HALIGN_MASK_SFT (0x1 << 4)
1756 #define IRQ31_MCU_ON_MASK 0x1
1757 #define IRQ31_MCU_ON_MASK_SFT (0x1 << 31)
1759 #define IRQ26_MCU_ON_MASK 0x1
1760 #define IRQ26_MCU_ON_MASK_SFT (0x1 << 26)
1762 #define IRQ25_MCU_ON_MASK 0x1
1763 #define IRQ25_MCU_ON_MASK_SFT (0x1 << 25)
1765 #define IRQ24_MCU_ON_MASK 0x1
1766 #define IRQ24_MCU_ON_MASK_SFT (0x1 << 24)
1768 #define IRQ23_MCU_ON_MASK 0x1
1769 #define IRQ23_MCU_ON_MASK_SFT (0x1 << 23)
1771 #define IRQ22_MCU_ON_MASK 0x1
1772 #define IRQ22_MCU_ON_MASK_SFT (0x1 << 22)
1774 #define IRQ21_MCU_ON_MASK 0x1
1775 #define IRQ21_MCU_ON_MASK_SFT (0x1 << 21)
1777 #define IRQ20_MCU_ON_MASK 0x1
1778 #define IRQ20_MCU_ON_MASK_SFT (0x1 << 20)
1780 #define IRQ19_MCU_ON_MASK 0x1
1781 #define IRQ19_MCU_ON_MASK_SFT (0x1 << 19)
1783 #define IRQ18_MCU_ON_MASK 0x1
1784 #define IRQ18_MCU_ON_MASK_SFT (0x1 << 18)
1786 #define IRQ17_MCU_ON_MASK 0x1
1787 #define IRQ17_MCU_ON_MASK_SFT (0x1 << 17)
1789 #define IRQ16_MCU_ON_MASK 0x1
1790 #define IRQ16_MCU_ON_MASK_SFT (0x1 << 16)
1792 #define IRQ15_MCU_ON_MASK 0x1
1793 #define IRQ15_MCU_ON_MASK_SFT (0x1 << 15)
1795 #define IRQ14_MCU_ON_MASK 0x1
1796 #define IRQ14_MCU_ON_MASK_SFT (0x1 << 14)
1798 #define IRQ13_MCU_ON_MASK 0x1
1799 #define IRQ13_MCU_ON_MASK_SFT (0x1 << 13)
1801 #define IRQ12_MCU_ON_MASK 0x1
1802 #define IRQ12_MCU_ON_MASK_SFT (0x1 << 12)
1804 #define IRQ11_MCU_ON_MASK 0x1
1805 #define IRQ11_MCU_ON_MASK_SFT (0x1 << 11)
1807 #define IRQ10_MCU_ON_MASK 0x1
1808 #define IRQ10_MCU_ON_MASK_SFT (0x1 << 10)
1810 #define IRQ9_MCU_ON_MASK 0x1
1811 #define IRQ9_MCU_ON_MASK_SFT (0x1 << 9)
1813 #define IRQ8_MCU_ON_MASK 0x1
1814 #define IRQ8_MCU_ON_MASK_SFT (0x1 << 8)
1816 #define IRQ7_MCU_ON_MASK 0x1
1817 #define IRQ7_MCU_ON_MASK_SFT (0x1 << 7)
1819 #define IRQ6_MCU_ON_MASK 0x1
1820 #define IRQ6_MCU_ON_MASK_SFT (0x1 << 6)
1822 #define IRQ5_MCU_ON_MASK 0x1
1823 #define IRQ5_MCU_ON_MASK_SFT (0x1 << 5)
1825 #define IRQ4_MCU_ON_MASK 0x1
1826 #define IRQ4_MCU_ON_MASK_SFT (0x1 << 4)
1828 #define IRQ3_MCU_ON_MASK 0x1
1829 #define IRQ3_MCU_ON_MASK_SFT (0x1 << 3)
1831 #define IRQ2_MCU_ON_MASK 0x1
1832 #define IRQ2_MCU_ON_MASK_SFT (0x1 << 2)
1834 #define IRQ1_MCU_ON_MASK 0x1
1835 #define IRQ1_MCU_ON_MASK_SFT (0x1 << 1)
1837 #define IRQ0_MCU_ON_MASK 0x1
1838 #define IRQ0_MCU_ON_MASK_SFT (0x1 << 0)
1931 #define IRQ31_MCU_CLR_MASK 0x1
1932 #define IRQ31_MCU_CLR_MASK_SFT (0x1 << 31)
1934 #define IRQ26_MCU_CLR_MASK 0x1
1935 #define IRQ26_MCU_CLR_MASK_SFT (0x1 << 26)
1937 #define IRQ25_MCU_CLR_MASK 0x1
1938 #define IRQ25_MCU_CLR_MASK_SFT (0x1 << 25)
1940 #define IRQ24_MCU_CLR_MASK 0x1
1941 #define IRQ24_MCU_CLR_MASK_SFT (0x1 << 24)
1943 #define IRQ23_MCU_CLR_MASK 0x1
1944 #define IRQ23_MCU_CLR_MASK_SFT (0x1 << 23)
1946 #define IRQ22_MCU_CLR_MASK 0x1
1947 #define IRQ22_MCU_CLR_MASK_SFT (0x1 << 22)
1949 #define IRQ21_MCU_CLR_MASK 0x1
1950 #define IRQ21_MCU_CLR_MASK_SFT (0x1 << 21)
1952 #define IRQ20_MCU_CLR_MASK 0x1
1953 #define IRQ20_MCU_CLR_MASK_SFT (0x1 << 20)
1955 #define IRQ19_MCU_CLR_MASK 0x1
1956 #define IRQ19_MCU_CLR_MASK_SFT (0x1 << 19)
1958 #define IRQ18_MCU_CLR_MASK 0x1
1959 #define IRQ18_MCU_CLR_MASK_SFT (0x1 << 18)
1961 #define IRQ17_MCU_CLR_MASK 0x1
1962 #define IRQ17_MCU_CLR_MASK_SFT (0x1 << 17)
1964 #define IRQ16_MCU_CLR_MASK 0x1
1965 #define IRQ16_MCU_CLR_MASK_SFT (0x1 << 16)
1967 #define IRQ15_MCU_CLR_MASK 0x1
1968 #define IRQ15_MCU_CLR_MASK_SFT (0x1 << 15)
1970 #define IRQ14_MCU_CLR_MASK 0x1
1971 #define IRQ14_MCU_CLR_MASK_SFT (0x1 << 14)
1973 #define IRQ13_MCU_CLR_MASK 0x1
1974 #define IRQ13_MCU_CLR_MASK_SFT (0x1 << 13)
1976 #define IRQ12_MCU_CLR_MASK 0x1
1977 #define IRQ12_MCU_CLR_MASK_SFT (0x1 << 12)
1979 #define IRQ11_MCU_CLR_MASK 0x1
1980 #define IRQ11_MCU_CLR_MASK_SFT (0x1 << 11)
1982 #define IRQ10_MCU_CLR_MASK 0x1
1983 #define IRQ10_MCU_CLR_MASK_SFT (0x1 << 10)
1985 #define IRQ9_MCU_CLR_MASK 0x1
1986 #define IRQ9_MCU_CLR_MASK_SFT (0x1 << 9)
1988 #define IRQ8_MCU_CLR_MASK 0x1
1989 #define IRQ8_MCU_CLR_MASK_SFT (0x1 << 8)
1991 #define IRQ7_MCU_CLR_MASK 0x1
1992 #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 7)
1994 #define IRQ6_MCU_CLR_MASK 0x1
1995 #define IRQ6_MCU_CLR_MASK_SFT (0x1 << 6)
1997 #define IRQ5_MCU_CLR_MASK 0x1
1998 #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 5)
2000 #define IRQ4_MCU_CLR_MASK 0x1
2001 #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 4)
2003 #define IRQ3_MCU_CLR_MASK 0x1
2004 #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 3)
2006 #define IRQ2_MCU_CLR_MASK 0x1
2007 #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 2)
2009 #define IRQ1_MCU_CLR_MASK 0x1
2010 #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 1)
2012 #define IRQ0_MCU_CLR_MASK 0x1
2013 #define IRQ0_MCU_CLR_MASK_SFT (0x1 << 0)
2085 #define TDM_EN_MASK 0x1
2086 #define TDM_EN_MASK_SFT (0x1 << 0)
2088 #define LRCK_INVERSE_MASK 0x1
2089 #define LRCK_INVERSE_MASK_SFT (0x1 << 2)
2091 #define DELAY_DATA_MASK 0x1
2092 #define DELAY_DATA_MASK_SFT (0x1 << 3)
2094 #define LEFT_ALIGN_MASK 0x1
2095 #define LEFT_ALIGN_MASK_SFT (0x1 << 4)
2126 #define TDM_FIX_VALUE_SEL_MASK 0x1
2127 #define TDM_FIX_VALUE_SEL_MASK_SFT (0x1 << 16)
2129 #define TDM_I2S_LOOPBACK_MASK 0x1
2130 #define TDM_I2S_LOOPBACK_MASK_SFT (0x1 << 20)
2172 #define RG_RX_PROTOCOL2_MASK 0x1
2173 #define RG_RX_PROTOCOL2_MASK_SFT (0x1 << 3)
2178 #define RG_RX_FIFO_ON_MASK 0x1
2179 #define RG_RX_FIFO_ON_MASK_SFT (0x1 << 0)
2183 #define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK 0x1
2184 #define RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 23)
2191 #define MTKAIF_RXIF_DETECT_ON_MASK 0x1
2192 #define MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 16)
2200 #define MTKAIF_RXIF_DATA_MODE_MASK 0x1
2201 #define MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
2219 #define GENERAL2_ASRC_EN_ON_MASK 0x1
2220 #define GENERAL2_ASRC_EN_ON_MASK_SFT (0x1 << 1)
2222 #define GENERAL1_ASRC_EN_ON_MASK 0x1
2223 #define GENERAL1_ASRC_EN_ON_MASK_SFT (0x1 << 0)
2227 #define G_SRC_CHSET_STR_CLR_MASK 0x1
2228 #define G_SRC_CHSET_STR_CLR_MASK_SFT (0x1 << 4)
2230 #define G_SRC_CHSET_ON_MASK 0x1
2231 #define G_SRC_CHSET_ON_MASK_SFT (0x1 << 2)
2233 #define G_SRC_COEFF_SRAM_CTRL_MASK 0x1
2234 #define G_SRC_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
2236 #define G_SRC_ASM_ON_MASK 0x1
2237 #define G_SRC_ASM_ON_MASK_SFT (0x1 << 0)
2256 #define G_SRC_CHSET_O16BIT_MASK 0x1
2257 #define G_SRC_CHSET_O16BIT_MASK_SFT (0x1 << 19)
2259 #define G_SRC_CHSET_CLR_IIR_HISTORY_MASK 0x1
2260 #define G_SRC_CHSET_CLR_IIR_HISTORY_MASK_SFT (0x1 << 17)
2262 #define G_SRC_CHSET_IS_MONO_MASK 0x1
2263 #define G_SRC_CHSET_IS_MONO_MASK_SFT (0x1 << 16)
2265 #define G_SRC_CHSET_IIR_EN_MASK 0x1
2266 #define G_SRC_CHSET_IIR_EN_MASK_SFT (0x1 << 11)
2271 #define G_SRC_CHSET_STR_CLR_RU_MASK 0x1
2272 #define G_SRC_CHSET_STR_CLR_RU_MASK_SFT (0x1 << 5)
2274 #define G_SRC_CHSET_ON_MASK 0x1
2275 #define G_SRC_CHSET_ON_MASK_SFT (0x1 << 2)
2277 #define G_SRC_COEFF_SRAM_CTRL_MASK 0x1
2278 #define G_SRC_COEFF_SRAM_CTRL_MASK_SFT (0x1 << 1)
2280 #define G_SRC_ASM_ON_MASK 0x1
2281 #define G_SRC_ASM_ON_MASK_SFT (0x1 << 0)
2285 #define ADDA_SDM_AUTO_RESET_ONOFF_MASK 0x1
2286 #define ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT (0x1 << 31)
2290 #define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK 0x1
2291 #define ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT (0x1 << 31)
2324 #define VUL6_USE_TINY_MASK_SFT (0x1 << 8)
2327 #define VUL5_USE_TINY_MASK_SFT (0x1 << 7)
2330 #define VUL4_USE_TINY_MASK_SFT (0x1 << 6)
2333 #define VUL3_USE_TINY_MASK_SFT (0x1 << 5)
2336 #define AWB2_USE_TINY_MASK_SFT (0x1 << 4)
2339 #define AWB_USE_TINY_MASK_SFT (0x1 << 3)
2342 #define VUL12_USE_TINY_MASK_SFT (0x1 << 2)
2345 #define VUL2_USE_TINY_MASK_SFT (0x1 << 1)
2348 #define VUL1_USE_TINY_MASK_SFT (0x1 << 0)
2353 #define CON0_CHSET_STR_CLR_MASK_SFT (0x1 << 4)
2356 #define CON0_ASM_ON_MASK_SFT (0x1 << 0)
2361 #define CALI_EN_MASK_SFT (0x1 << 0)