Lines Matching full:x1
263 #define AHB_IDLE_EN_INT_MASK 0x1
264 #define AHB_IDLE_EN_INT_MASK_SFT (0x1 << 30)
266 #define AHB_IDLE_EN_EXT_MASK 0x1
267 #define AHB_IDLE_EN_EXT_MASK_SFT (0x1 << 29)
269 #define PDN_TML_MASK 0x1
270 #define PDN_TML_MASK_SFT (0x1 << 27)
272 #define PDN_DAC_PREDIS_MASK 0x1
273 #define PDN_DAC_PREDIS_MASK_SFT (0x1 << 26)
275 #define PDN_DAC_MASK 0x1
276 #define PDN_DAC_MASK_SFT (0x1 << 25)
278 #define PDN_ADC_MASK 0x1
279 #define PDN_ADC_MASK_SFT (0x1 << 24)
281 #define PDN_TDM_CK_MASK 0x1
282 #define PDN_TDM_CK_MASK_SFT (0x1 << 20)
284 #define PDN_APLL_TUNER_MASK 0x1
285 #define PDN_APLL_TUNER_MASK_SFT (0x1 << 19)
287 #define PDN_APLL2_TUNER_MASK 0x1
288 #define PDN_APLL2_TUNER_MASK_SFT (0x1 << 18)
290 #define APB3_SEL_MASK 0x1
291 #define APB3_SEL_MASK_SFT (0x1 << 14)
293 #define APB_R2T_MASK 0x1
294 #define APB_R2T_MASK_SFT (0x1 << 13)
296 #define APB_W2T_MASK 0x1
297 #define APB_W2T_MASK_SFT (0x1 << 12)
299 #define PDN_24M_MASK 0x1
300 #define PDN_24M_MASK_SFT (0x1 << 9)
302 #define PDN_22M_MASK 0x1
303 #define PDN_22M_MASK_SFT (0x1 << 8)
305 #define PDN_ADDA4_ADC_MASK 0x1
306 #define PDN_ADDA4_ADC_MASK_SFT (0x1 << 7)
308 #define PDN_I2S_MASK 0x1
309 #define PDN_I2S_MASK_SFT (0x1 << 6)
311 #define PDN_AFE_MASK 0x1
312 #define PDN_AFE_MASK_SFT (0x1 << 2)
316 #define PDN_ADC_HIRES_TML_MASK 0x1
317 #define PDN_ADC_HIRES_TML_MASK_SFT (0x1 << 17)
319 #define PDN_ADC_HIRES_MASK 0x1
320 #define PDN_ADC_HIRES_MASK_SFT (0x1 << 16)
322 #define I2S4_BCLK_SW_CG_MASK 0x1
323 #define I2S4_BCLK_SW_CG_MASK_SFT (0x1 << 7)
325 #define I2S3_BCLK_SW_CG_MASK 0x1
326 #define I2S3_BCLK_SW_CG_MASK_SFT (0x1 << 6)
328 #define I2S2_BCLK_SW_CG_MASK 0x1
329 #define I2S2_BCLK_SW_CG_MASK_SFT (0x1 << 5)
331 #define I2S1_BCLK_SW_CG_MASK 0x1
332 #define I2S1_BCLK_SW_CG_MASK_SFT (0x1 << 4)
334 #define I2S_SOFT_RST2_MASK 0x1
335 #define I2S_SOFT_RST2_MASK_SFT (0x1 << 2)
337 #define I2S_SOFT_RST_MASK 0x1
338 #define I2S_SOFT_RST_MASK_SFT (0x1 << 1)
342 #define AFE_AWB_RETM_MASK 0x1
343 #define AFE_AWB_RETM_MASK_SFT (0x1 << 31)
345 #define AFE_DL1_DATA2_RETM_MASK 0x1
346 #define AFE_DL1_DATA2_RETM_MASK_SFT (0x1 << 30)
348 #define AFE_DL2_RETM_MASK 0x1
349 #define AFE_DL2_RETM_MASK_SFT (0x1 << 29)
351 #define AFE_DL1_RETM_MASK 0x1
352 #define AFE_DL1_RETM_MASK_SFT (0x1 << 28)
354 #define AFE_ON_RETM_MASK 0x1
355 #define AFE_ON_RETM_MASK_SFT (0x1 << 27)
357 #define MOD_DAI_DUP_WR_MASK 0x1
358 #define MOD_DAI_DUP_WR_MASK_SFT (0x1 << 26)
372 #define VUL_DATA2_R_MONO_MASK 0x1
373 #define VUL_DATA2_R_MONO_MASK_SFT (0x1 << 11)
375 #define VUL_DATA2_DATA_MASK 0x1
376 #define VUL_DATA2_DATA_MASK_SFT (0x1 << 10)
378 #define VUL_DATA2_ON_MASK 0x1
379 #define VUL_DATA2_ON_MASK_SFT (0x1 << 9)
381 #define DL1_DATA2_ON_MASK 0x1
382 #define DL1_DATA2_ON_MASK_SFT (0x1 << 8)
384 #define MOD_DAI_ON_MASK 0x1
385 #define MOD_DAI_ON_MASK_SFT (0x1 << 7)
387 #define AWB_ON_MASK 0x1
388 #define AWB_ON_MASK_SFT (0x1 << 6)
390 #define DL3_ON_MASK 0x1
391 #define DL3_ON_MASK_SFT (0x1 << 5)
393 #define DAI_ON_MASK 0x1
394 #define DAI_ON_MASK_SFT (0x1 << 4)
396 #define VUL_ON_MASK 0x1
397 #define VUL_ON_MASK_SFT (0x1 << 3)
399 #define DL2_ON_MASK 0x1
400 #define DL2_ON_MASK_SFT (0x1 << 2)
402 #define DL1_ON_MASK 0x1
403 #define DL1_ON_MASK_SFT (0x1 << 1)
405 #define AFE_ON_MASK 0x1
406 #define AFE_ON_MASK_SFT (0x1 << 0)
413 #define DAI_DUP_WR_MASK 0x1
414 #define DAI_DUP_WR_MASK_SFT (0x1 << 29)
416 #define VUL_R_MONO_MASK 0x1
417 #define VUL_R_MONO_MASK_SFT (0x1 << 28)
419 #define VUL_DATA_MASK 0x1
420 #define VUL_DATA_MASK_SFT (0x1 << 27)
422 #define AXI_2X1_CG_DISABLE_MASK 0x1
423 #define AXI_2X1_CG_DISABLE_MASK_SFT (0x1 << 26)
425 #define AWB_R_MONO_MASK 0x1
426 #define AWB_R_MONO_MASK_SFT (0x1 << 25)
428 #define AWB_DATA_MASK 0x1
429 #define AWB_DATA_MASK_SFT (0x1 << 24)
431 #define DL3_DATA_MASK 0x1
432 #define DL3_DATA_MASK_SFT (0x1 << 23)
434 #define DL2_DATA_MASK 0x1
435 #define DL2_DATA_MASK_SFT (0x1 << 22)
437 #define DL1_DATA_MASK 0x1
438 #define DL1_DATA_MASK_SFT (0x1 << 21)
440 #define DL1_DATA2_DATA_MASK 0x1
441 #define DL1_DATA2_DATA_MASK_SFT (0x1 << 20)
463 #define DL_2_CH1_SATURATION_EN_CTL_MASK 0x1
464 #define DL_2_CH1_SATURATION_EN_CTL_MASK_SFT (0x1 << 27)
466 #define DL_2_CH2_SATURATION_EN_CTL_MASK 0x1
467 #define DL_2_CH2_SATURATION_EN_CTL_MASK_SFT (0x1 << 26)
475 #define DL_DISABLE_HW_CG_CTL_MASK 0x1
476 #define DL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 15)
478 #define C_DATA_EN_SEL_CTL_PRE_MASK 0x1
479 #define C_DATA_EN_SEL_CTL_PRE_MASK_SFT (0x1 << 14)
481 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK 0x1
482 #define DL_2_SIDE_TONE_ON_CTL_PRE_MASK_SFT (0x1 << 13)
484 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK 0x1
485 #define DL_2_MUTE_CH1_OFF_CTL_PRE_MASK_SFT (0x1 << 12)
487 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK 0x1
488 #define DL_2_MUTE_CH2_OFF_CTL_PRE_MASK_SFT (0x1 << 11)
496 #define DL_2_VOICE_MODE_CTL_PRE_MASK 0x1
497 #define DL_2_VOICE_MODE_CTL_PRE_MASK_SFT (0x1 << 5)
499 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK 0x1
500 #define D2_2_MUTE_CH1_ON_CTL_PRE_MASK_SFT (0x1 << 4)
502 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK 0x1
503 #define D2_2_MUTE_CH2_ON_CTL_PRE_MASK_SFT (0x1 << 3)
505 #define DL_2_IIR_ON_CTL_PRE_MASK 0x1
506 #define DL_2_IIR_ON_CTL_PRE_MASK_SFT (0x1 << 2)
508 #define DL_2_GAIN_ON_CTL_PRE_MASK 0x1
509 #define DL_2_GAIN_ON_CTL_PRE_MASK_SFT (0x1 << 1)
511 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
512 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
519 #define DL_2_GAIN_MODE_CTL_MASK 0x1
520 #define DL_2_GAIN_MODE_CTL_MASK_SFT (0x1 << 0)
524 #define C_COMB_OUT_SIN_GEN_CTL_MASK 0x1
525 #define C_COMB_OUT_SIN_GEN_CTL_MASK_SFT (0x1 << 31)
527 #define C_BASEBAND_SIN_GEN_CTL_MASK 0x1
528 #define C_BASEBAND_SIN_GEN_CTL_MASK_SFT (0x1 << 30)
536 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
537 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 23)
539 #define UL_MODE_3P25M_CH2_CTL_MASK 0x1
540 #define UL_MODE_3P25M_CH2_CTL_MASK_SFT (0x1 << 22)
542 #define UL_MODE_3P25M_CH1_CTL_MASK 0x1
543 #define UL_MODE_3P25M_CH1_CTL_MASK_SFT (0x1 << 21)
545 #define UL_SRC_USE_CIC_OUT_CTL_MASK 0x1
546 #define UL_SRC_USE_CIC_OUT_CTL_MASK_SFT (0x1 << 20)
554 #define DMIC_48K_SEL_CTL_MASK 0x1
555 #define DMIC_48K_SEL_CTL_MASK_SFT (0x1 << 13)
557 #define UL_DISABLE_HW_CG_CTL_MASK 0x1
558 #define UL_DISABLE_HW_CG_CTL_MASK_SFT (0x1 << 12)
560 #define UL_IIR_ON_TMP_CTL_MASK 0x1
561 #define UL_IIR_ON_TMP_CTL_MASK_SFT (0x1 << 10)
566 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
567 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
569 #define AGC_260K_SEL_CH2_CTL_MASK 0x1
570 #define AGC_260K_SEL_CH2_CTL_MASK_SFT (0x1 << 4)
572 #define AGC_260K_SEL_CH1_CTL_MASK 0x1
573 #define AGC_260K_SEL_CH1_CTL_MASK_SFT (0x1 << 3)
575 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
576 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
578 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
579 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
581 #define UL_SRC_ON_TMP_CTL_MASK 0x1
582 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
586 #define C_SDM_RESET_CTL_MASK 0x1
587 #define C_SDM_RESET_CTL_MASK_SFT (0x1 << 31)
589 #define ADITHON_CTL_MASK 0x1
590 #define ADITHON_CTL_MASK_SFT (0x1 << 30)
595 #define C_DAC_EN_CTL_MASK 0x1
596 #define C_DAC_EN_CTL_MASK_SFT (0x1 << 27)
598 #define C_MUTE_SW_CTL_MASK 0x1
599 #define C_MUTE_SW_CTL_MASK_SFT (0x1 << 26)
601 #define ASDM_SRC_SEL_CTL_MASK 0x1
602 #define ASDM_SRC_SEL_CTL_MASK_SFT (0x1 << 25)
627 #define C_EXT_ADC_CTL_MASK 0x1
628 #define C_EXT_ADC_CTL_MASK_SFT (0x1 << 0)
635 #define ADDA_AFE_ON_MASK 0x1
636 #define ADDA_AFE_ON_MASK_SFT (0x1 << 0)
649 #define IRQ7_MCU_ON_MASK 0x1
650 #define IRQ7_MCU_ON_MASK_SFT (0x1 << 14)
652 #define IRQ5_MCU_ON_MASK 0x1
653 #define IRQ5_MCU_ON_MASK_SFT (0x1 << 12)
661 #define IRQ4_MCU_ON_MASK 0x1
662 #define IRQ4_MCU_ON_MASK_SFT (0x1 << 3)
664 #define IRQ3_MCU_ON_MASK 0x1
665 #define IRQ3_MCU_ON_MASK_SFT (0x1 << 2)
667 #define IRQ2_MCU_ON_MASK 0x1
668 #define IRQ2_MCU_ON_MASK_SFT (0x1 << 1)
670 #define IRQ1_MCU_ON_MASK 0x1
671 #define IRQ1_MCU_ON_MASK_SFT (0x1 << 0)
686 #define IRQ7_MCU_CLR_MASK 0x1
687 #define IRQ7_MCU_CLR_MASK_SFT (0x1 << 6)
689 #define IRQ5_MCU_CLR_MASK 0x1
690 #define IRQ5_MCU_CLR_MASK_SFT (0x1 << 4)
692 #define IRQ4_MCU_CLR_MASK 0x1
693 #define IRQ4_MCU_CLR_MASK_SFT (0x1 << 3)
695 #define IRQ3_MCU_CLR_MASK 0x1
696 #define IRQ3_MCU_CLR_MASK_SFT (0x1 << 2)
698 #define IRQ2_MCU_CLR_MASK 0x1
699 #define IRQ2_MCU_CLR_MASK_SFT (0x1 << 1)
701 #define IRQ1_MCU_CLR_MASK 0x1
702 #define IRQ1_MCU_CLR_MASK_SFT (0x1 << 0)
736 #define CPU_COMPACT_MODE_MASK 0x1
737 #define CPU_COMPACT_MODE_MASK_SFT (0x1 << 23)
739 #define CPU_HD_ALIGN_MASK 0x1
740 #define CPU_HD_ALIGN_MASK_SFT (0x1 << 22)
776 #define HDMI_NORMAL_MODE_MASK 0x1
777 #define HDMI_NORMAL_MODE_MASK_SFT (0x1 << 26)
779 #define MOD_DAI_NORMAL_MODE_MASK 0x1
780 #define MOD_DAI_NORMAL_MODE_MASK_SFT (0x1 << 25)
782 #define DAI_NORMAL_MODE_MASK 0x1
783 #define DAI_NORMAL_MODE_MASK_SFT (0x1 << 24)
785 #define VUL_DATA2_NORMAL_MODE_MASK 0x1
786 #define VUL_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 22)
788 #define VUL_NORMAL_MODE_MASK 0x1
789 #define VUL_NORMAL_MODE_MASK_SFT (0x1 << 21)
791 #define AWB_NORMAL_MODE_MASK 0x1
792 #define AWB_NORMAL_MODE_MASK_SFT (0x1 << 20)
794 #define DL3_NORMAL_MODE_MASK 0x1
795 #define DL3_NORMAL_MODE_MASK_SFT (0x1 << 19)
797 #define DL2_NORMAL_MODE_MASK 0x1
798 #define DL2_NORMAL_MODE_MASK_SFT (0x1 << 18)
800 #define DL1_DATA2_NORMAL_MODE_MASK 0x1
801 #define DL1_DATA2_NORMAL_MODE_MASK_SFT (0x1 << 17)
803 #define DL1_NORMAL_MODE_MASK 0x1
804 #define DL1_NORMAL_MODE_MASK_SFT (0x1 << 16)
806 #define HDMI_HD_ALIGN_MASK 0x1
807 #define HDMI_HD_ALIGN_MASK_SFT (0x1 << 10)
809 #define MOD_DAI_HD_ALIGN_MASK 0x1
810 #define MOD_DAI_HD_ALIGN_MASK_SFT (0x1 << 9)
812 #define DAI_ALIGN_MASK 0x1
813 #define DAI_ALIGN_MASK_SFT (0x1 << 8)
815 #define VUL2_HD_ALIGN_MASK 0x1
816 #define VUL2_HD_ALIGN_MASK_SFT (0x1 << 7)
818 #define VUL_DATA2_HD_ALIGN_MASK 0x1
819 #define VUL_DATA2_HD_ALIGN_MASK_SFT (0x1 << 6)
821 #define VUL_HD_ALIGN_MASK 0x1
822 #define VUL_HD_ALIGN_MASK_SFT (0x1 << 5)
824 #define AWB_HD_ALIGN_MASK 0x1
825 #define AWB_HD_ALIGN_MASK_SFT (0x1 << 4)
827 #define DL3_HD_ALIGN_MASK 0x1
828 #define DL3_HD_ALIGN_MASK_SFT (0x1 << 3)
830 #define DL2_HD_ALIGN_MASK 0x1
831 #define DL2_HD_ALIGN_MASK_SFT (0x1 << 2)
833 #define DL1_DATA2_HD_ALIGN_MASK 0x1
834 #define DL1_DATA2_HD_ALIGN_MASK_SFT (0x1 << 1)
836 #define DL1_HD_ALIGN_MASK 0x1
837 #define DL1_HD_ALIGN_MASK_SFT (0x1 << 0)
841 #define PCM_FIX_VALUE_SEL_MASK 0x1
842 #define PCM_FIX_VALUE_SEL_MASK_SFT (0x1 << 31)
844 #define PCM_BUFFER_LOOPBACK_MASK 0x1
845 #define PCM_BUFFER_LOOPBACK_MASK_SFT (0x1 << 30)
847 #define PCM_PARALLEL_LOOPBACK_MASK 0x1
848 #define PCM_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 29)
850 #define PCM_SERIAL_LOOPBACK_MASK 0x1
851 #define PCM_SERIAL_LOOPBACK_MASK_SFT (0x1 << 28)
853 #define PCM_DAI_PCM_LOOPBACK_MASK 0x1
854 #define PCM_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 27)
856 #define PCM_I2S_PCM_LOOPBACK_MASK 0x1
857 #define PCM_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 26)
859 #define PCM_SYNC_DELSEL_MASK 0x1
860 #define PCM_SYNC_DELSEL_MASK_SFT (0x1 << 25)
862 #define PCM_TX_LR_SWAP_MASK 0x1
863 #define PCM_TX_LR_SWAP_MASK_SFT (0x1 << 24)
865 #define PCM_SYNC_OUT_INV_MASK 0x1
866 #define PCM_SYNC_OUT_INV_MASK_SFT (0x1 << 23)
868 #define PCM_BCLK_OUT_INV_MASK 0x1
869 #define PCM_BCLK_OUT_INV_MASK_SFT (0x1 << 22)
871 #define PCM_SYNC_IN_INV_MASK 0x1
872 #define PCM_SYNC_IN_INV_MASK_SFT (0x1 << 21)
874 #define PCM_BCLK_IN_INV_MASK 0x1
875 #define PCM_BCLK_IN_INV_MASK_SFT (0x1 << 20)
877 #define PCM_TX_LCH_RPT_MASK 0x1
878 #define PCM_TX_LCH_RPT_MASK_SFT (0x1 << 19)
880 #define PCM_VBT_16K_MODE_MASK 0x1
881 #define PCM_VBT_16K_MODE_MASK_SFT (0x1 << 18)
883 #define PCM_EXT_MODEM_MASK 0x1
884 #define PCM_EXT_MODEM_MASK_SFT (0x1 << 17)
886 #define PCM_24BIT_MASK 0x1
887 #define PCM_24BIT_MASK_SFT (0x1 << 16)
895 #define PCM_SYNC_TYPE_MASK 0x1
896 #define PCM_SYNC_TYPE_MASK_SFT (0x1 << 8)
898 #define PCM_BT_MODE_MASK 0x1
899 #define PCM_BT_MODE_MASK_SFT (0x1 << 7)
901 #define PCM_BYP_ASRC_MASK 0x1
902 #define PCM_BYP_ASRC_MASK_SFT (0x1 << 6)
904 #define PCM_SLAVE_MASK 0x1
905 #define PCM_SLAVE_MASK_SFT (0x1 << 5)
913 #define PCM_EN_MASK 0x1
914 #define PCM_EN_MASK_SFT (0x1 << 0)
918 #define PCM1_TX_FIFO_OV_MASK 0x1
919 #define PCM1_TX_FIFO_OV_MASK_SFT (0x1 << 31)
921 #define PCM1_RX_FIFO_OV_MASK 0x1
922 #define PCM1_RX_FIFO_OV_MASK_SFT (0x1 << 30)
924 #define PCM2_TX_FIFO_OV_MASK 0x1
925 #define PCM2_TX_FIFO_OV_MASK_SFT (0x1 << 29)
927 #define PCM2_RX_FIFO_OV_MASK 0x1
928 #define PCM2_RX_FIFO_OV_MASK_SFT (0x1 << 28)
930 #define PCM1_SYNC_GLITCH_MASK 0x1
931 #define PCM1_SYNC_GLITCH_MASK_SFT (0x1 << 27)
933 #define PCM2_SYNC_GLITCH_MASK 0x1
934 #define PCM2_SYNC_GLITCH_MASK_SFT (0x1 << 26)
936 #define PCM1_PCM2_LOOPBACK_MASK 0x1
937 #define PCM1_PCM2_LOOPBACK_MASK_SFT (0x1 << 15)
939 #define DAI_PCM_LOOPBACK_CH_MASK 0x1
940 #define DAI_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 13)
942 #define I2S_PCM_LOOPBACK_CH_MASK 0x1
943 #define I2S_PCM_LOOPBACK_CH_MASK_SFT (0x1 << 12)
945 #define PCM_USE_MD3_MASK 0x1
946 #define PCM_USE_MD3_MASK_SFT (0x1 << 8)
956 #define PCM2_FIX_VALUE_SEL_MASK 0x1
957 #define PCM2_FIX_VALUE_SEL_MASK_SFT (0x1 << 23)
959 #define PCM2_BUFFER_LOOPBACK_MASK 0x1
960 #define PCM2_BUFFER_LOOPBACK_MASK_SFT (0x1 << 22)
962 #define PCM2_PARALLEL_LOOPBACK_MASK 0x1
963 #define PCM2_PARALLEL_LOOPBACK_MASK_SFT (0x1 << 21)
965 #define PCM2_SERIAL_LOOPBACK_MASK 0x1
966 #define PCM2_SERIAL_LOOPBACK_MASK_SFT (0x1 << 20)
968 #define PCM2_DAI_PCM_LOOPBACK_MASK 0x1
969 #define PCM2_DAI_PCM_LOOPBACK_MASK_SFT (0x1 << 19)
971 #define PCM2_I2S_PCM_LOOPBACK_MASK 0x1
972 #define PCM2_I2S_PCM_LOOPBACK_MASK_SFT (0x1 << 18)
974 #define PCM2_SYNC_DELSEL_MASK 0x1
975 #define PCM2_SYNC_DELSEL_MASK_SFT (0x1 << 17)
977 #define PCM2_TX_LR_SWAP_MASK 0x1
978 #define PCM2_TX_LR_SWAP_MASK_SFT (0x1 << 16)
980 #define PCM2_SYNC_IN_INV_MASK 0x1
981 #define PCM2_SYNC_IN_INV_MASK_SFT (0x1 << 15)
983 #define PCM2_BCLK_IN_INV_MASK 0x1
984 #define PCM2_BCLK_IN_INV_MASK_SFT (0x1 << 14)
986 #define PCM2_TX_LCH_RPT_MASK 0x1
987 #define PCM2_TX_LCH_RPT_MASK_SFT (0x1 << 13)
989 #define PCM2_VBT_16K_MODE_MASK 0x1
990 #define PCM2_VBT_16K_MODE_MASK_SFT (0x1 << 12)
995 #define PCM2_TX2_BT_MODE_MASK 0x1
996 #define PCM2_TX2_BT_MODE_MASK_SFT (0x1 << 8)
998 #define PCM2_BT_MODE_MASK 0x1
999 #define PCM2_BT_MODE_MASK_SFT (0x1 << 7)
1001 #define PCM2_AFIFO_MASK 0x1
1002 #define PCM2_AFIFO_MASK_SFT (0x1 << 6)
1004 #define PCM2_WLEN_MASK 0x1
1005 #define PCM2_WLEN_MASK_SFT (0x1 << 5)
1013 #define PCM2_EN_MASK 0x1
1014 #define PCM2_EN_MASK_SFT (0x1 << 0)