27 /* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
34 	struct clk *mclk;  member
66 		if (ctx->mclk) {  in platform_clock_control()
67 			ret = clk_prepare_enable(ctx->mclk);  in platform_clock_control()
70 					"could not configure MCLK state");  in platform_clock_control()
75 		/* set codec PLL source to the 19.2MHz platform clock (MCLK) */  in platform_clock_control()
92 		 * PLL will be off when idle and MCLK will also be off by ACPI  in platform_clock_control()
99 		if (ctx->mclk)  in platform_clock_control()
100 			clk_disable_unprepare(ctx->mclk);  in platform_clock_control()
162 	/* set codec PLL source to the 19.2MHz platform clock (MCLK) */  in cht_aif1_hw_params()
238 	if (ctx->mclk) {  in cht_codec_init()
249 		ret = clk_prepare_enable(ctx->mclk);  in cht_codec_init()
251 			clk_disable_unprepare(ctx->mclk);  in cht_codec_init()
253 		ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);  in cht_codec_init()
256 			dev_err(runtime->dev, "unable to set MCLK rate\n");  in cht_codec_init()
497 	drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");  in snd_cht_mc_probe()
498 	if (IS_ERR(drv->mclk)) {  in snd_cht_mc_probe()
500 			"Failed to get MCLK from pmc_plt_clk_3: %ld\n",  in snd_cht_mc_probe()
501 			PTR_ERR(drv->mclk));  in snd_cht_mc_probe()
502 		return PTR_ERR(drv->mclk);  in snd_cht_mc_probe()