Lines Matching refs:chv3_i2s_wr
101 static inline void chv3_i2s_wr(struct chv3_i2s_dev *i2s, int offset, u32 val) in chv3_i2s_wr() function
159 chv3_i2s_wr(i2s, I2S_RX_ENABLE, 0); in chv3_dma_close()
161 chv3_i2s_wr(i2s, I2S_TX_ENABLE, 0); in chv3_dma_close()
212 chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_RX_BIT); in chv3_dma_prepare()
213 chv3_i2s_wr(i2s, I2S_RX_BASE_ADDR, substream->dma_buffer.addr); in chv3_dma_prepare()
214 chv3_i2s_wr(i2s, I2S_RX_BUFFER_SIZE, buffer_bytes); in chv3_dma_prepare()
215 chv3_i2s_wr(i2s, I2S_RX_IRQ, (period_size << 8) | 1); in chv3_dma_prepare()
216 chv3_i2s_wr(i2s, I2S_RX_ENABLE, 1); in chv3_dma_prepare()
218 chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_TX_BIT); in chv3_dma_prepare()
219 chv3_i2s_wr(i2s, I2S_TX_BASE_ADDR, substream->dma_buffer.addr); in chv3_dma_prepare()
220 chv3_i2s_wr(i2s, I2S_TX_BUFFER_SIZE, buffer_bytes); in chv3_dma_prepare()
221 chv3_i2s_wr(i2s, I2S_TX_IRQ, ((period_bytes / i2s->tx_bytes_to_fetch) << 8) | 1); in chv3_dma_prepare()
222 chv3_i2s_wr(i2s, I2S_TX_ENABLE, 1); in chv3_dma_prepare()
263 chv3_i2s_wr(i2s, I2S_RX_CONSUMER_IDX, idx); in chv3_dma_ack()
265 chv3_i2s_wr(i2s, I2S_TX_PRODUCER_IDX, idx); in chv3_dma_ack()