Lines Matching refs:u32
38 u32 mode;
39 u32 arc_mode;
50 u32 mfn; /* signed int, 2's compl., min=0x3FFF0000, max=0x00010000 */
51 u32 mfd; /* unsigned int */
52 u32 fout; /* Fout = Fref*(MFI + MFN/MFD), Fref is 24MHz */
64 static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, };
70 static const u32 fsl_xcvr_earc_rates[] = {
80 static const u32 fsl_xcvr_spdif_channels[] = { 2, };
86 static const u32 fsl_xcvr_spdif_rates[] = {
118 static const u32 fsl_xcvr_phy_arc_cfg[] = {
239 static int fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy) in fsl_xcvr_ai_write()
242 u32 val, idx, tidx; in fsl_xcvr_ai_write()
262 static int fsl_xcvr_en_phy_pll(struct fsl_xcvr *xcvr, u32 freq, bool tx) in fsl_xcvr_en_phy_pll()
265 u32 i, div = 0, log2; in fsl_xcvr_en_phy_pll()
358 static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq) in fsl_xcvr_en_aud_pll()
412 u32 m_ctl = 0, v_ctl = 0; in fsl_xcvr_prepare()
413 u32 r = substream->runtime->rate, ch = substream->runtime->channels; in fsl_xcvr_prepare()
414 u32 fout = 32 * r * ch * 10; in fsl_xcvr_prepare()
599 u32 mask = 0, val = 0; in fsl_xcvr_shutdown()
747 u32 mask, val; in fsl_xcvr_load_firmware()
1165 u32 isr, isr_clr = 0, val, i; in irq0_isr()
1193 val = *(u32 *)(xcvr->rx_iec958.status + i*4); in irq0_isr()
1194 *(u32 *)(xcvr->rx_iec958.status + i*4) = in irq0_isr()