Lines Matching refs:i2s_write_reg
31 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val) in i2s_write_reg() function
47 i2s_write_reg(dev->i2s_base, TER(i), 0); in i2s_disable_channels()
50 i2s_write_reg(dev->i2s_base, RER(i), 0); in i2s_disable_channels()
75 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); in i2s_disable_irqs()
80 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); in i2s_disable_irqs()
93 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); in i2s_enable_irqs()
98 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); in i2s_enable_irqs()
164 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); in i2s_enable_dma()
174 i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1); in i2s_disable_dma()
177 i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1); in i2s_disable_dma()
179 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); in i2s_disable_dma()
195 i2s_write_reg(dev->i2s_base, IER, reg); in i2s_start()
198 i2s_write_reg(dev->i2s_base, ITER, 1); in i2s_start()
200 i2s_write_reg(dev->i2s_base, IRER, 1); in i2s_start()
208 i2s_write_reg(dev->i2s_base, CER, 1); in i2s_start()
217 i2s_write_reg(dev->i2s_base, ITER, 0); in i2s_stop()
219 i2s_write_reg(dev->i2s_base, IRER, 0); in i2s_stop()
227 i2s_write_reg(dev->i2s_base, CER, 0); in i2s_stop()
228 i2s_write_reg(dev->i2s_base, IER, 0); in i2s_stop()
257 i2s_write_reg(dev->i2s_base, TCR(ch_reg), in dw_i2s_config()
259 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), in dw_i2s_config()
261 i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN | in dw_i2s_config()
264 i2s_write_reg(dev->i2s_base, RCR(ch_reg), in dw_i2s_config()
266 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), in dw_i2s_config()
268 i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN | in dw_i2s_config()
324 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); in dw_i2s_hw_params()
356 i2s_write_reg(dev->i2s_base, TXFFR, 1); in dw_i2s_prepare()
358 i2s_write_reg(dev->i2s_base, RXFFR, 1); in dw_i2s_prepare()