Lines Matching refs:dev
41 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream) in i2s_disable_channels() argument
47 i2s_write_reg(dev->i2s_base, TER(i), 0); in i2s_disable_channels()
50 i2s_write_reg(dev->i2s_base, RER(i), 0); in i2s_disable_channels()
54 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream) in i2s_clear_irqs() argument
60 i2s_read_reg(dev->i2s_base, TOR(i)); in i2s_clear_irqs()
63 i2s_read_reg(dev->i2s_base, ROR(i)); in i2s_clear_irqs()
67 static inline void i2s_disable_irqs(struct dw_i2s_dev *dev, u32 stream, in i2s_disable_irqs() argument
74 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
75 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30); in i2s_disable_irqs()
79 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_disable_irqs()
80 i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03); in i2s_disable_irqs()
85 static inline void i2s_enable_irqs(struct dw_i2s_dev *dev, u32 stream, in i2s_enable_irqs() argument
92 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_enable_irqs()
93 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30); in i2s_enable_irqs()
97 irq = i2s_read_reg(dev->i2s_base, IMR(i)); in i2s_enable_irqs()
98 i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03); in i2s_enable_irqs()
105 struct dw_i2s_dev *dev = dev_id; in i2s_irq_handler() local
111 isr[i] = i2s_read_reg(dev->i2s_base, ISR(i)); in i2s_irq_handler()
113 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_PLAYBACK); in i2s_irq_handler()
114 i2s_clear_irqs(dev, SNDRV_PCM_STREAM_CAPTURE); in i2s_irq_handler()
121 if ((isr[i] & ISR_TXFE) && (i == 0) && dev->use_pio) { in i2s_irq_handler()
122 dw_pcm_push_tx(dev); in i2s_irq_handler()
130 if ((isr[i] & ISR_RXDA) && (i == 0) && dev->use_pio) { in i2s_irq_handler()
131 dw_pcm_pop_rx(dev); in i2s_irq_handler()
137 dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); in i2s_irq_handler()
143 dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); in i2s_irq_handler()
154 static void i2s_enable_dma(struct dw_i2s_dev *dev, u32 stream) in i2s_enable_dma() argument
156 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); in i2s_enable_dma()
164 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); in i2s_enable_dma()
167 static void i2s_disable_dma(struct dw_i2s_dev *dev, u32 stream) in i2s_disable_dma() argument
169 u32 dma_reg = i2s_read_reg(dev->i2s_base, I2S_DMACR); in i2s_disable_dma()
174 i2s_write_reg(dev->i2s_base, I2S_RTXDMA, 1); in i2s_disable_dma()
177 i2s_write_reg(dev->i2s_base, I2S_RRXDMA, 1); in i2s_disable_dma()
179 i2s_write_reg(dev->i2s_base, I2S_DMACR, dma_reg); in i2s_disable_dma()
182 static void i2s_start(struct dw_i2s_dev *dev, in i2s_start() argument
185 struct i2s_clk_config_data *config = &dev->config; in i2s_start()
189 if (dev->tdm_slots) { in i2s_start()
190 reg |= (dev->tdm_slots - 1) << IER_TDM_SLOTS_SHIFT; in i2s_start()
192 reg |= dev->frame_offset << IER_FRAME_OFF_SHIFT; in i2s_start()
195 i2s_write_reg(dev->i2s_base, IER, reg); in i2s_start()
198 i2s_write_reg(dev->i2s_base, ITER, 1); in i2s_start()
200 i2s_write_reg(dev->i2s_base, IRER, 1); in i2s_start()
203 if (dev->use_pio || dev->is_jh7110) in i2s_start()
204 i2s_enable_irqs(dev, substream->stream, config->chan_nr); in i2s_start()
206 i2s_enable_dma(dev, substream->stream); in i2s_start()
208 i2s_write_reg(dev->i2s_base, CER, 1); in i2s_start()
211 static void i2s_stop(struct dw_i2s_dev *dev, in i2s_stop() argument
215 i2s_clear_irqs(dev, substream->stream); in i2s_stop()
217 i2s_write_reg(dev->i2s_base, ITER, 0); in i2s_stop()
219 i2s_write_reg(dev->i2s_base, IRER, 0); in i2s_stop()
221 if (dev->use_pio || dev->is_jh7110) in i2s_stop()
222 i2s_disable_irqs(dev, substream->stream, 8); in i2s_stop()
224 i2s_disable_dma(dev, substream->stream); in i2s_stop()
226 if (!dev->active) { in i2s_stop()
227 i2s_write_reg(dev->i2s_base, CER, 0); in i2s_stop()
228 i2s_write_reg(dev->i2s_base, IER, 0); in i2s_stop()
235 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); in dw_i2s_startup() local
237 if (dev->is_jh7110) { in dw_i2s_startup()
247 static void dw_i2s_config(struct dw_i2s_dev *dev, int stream) in dw_i2s_config() argument
250 struct i2s_clk_config_data *config = &dev->config; in dw_i2s_config()
253 i2s_disable_channels(dev, stream); in dw_i2s_config()
257 i2s_write_reg(dev->i2s_base, TCR(ch_reg), in dw_i2s_config()
258 dev->xfer_resolution); in dw_i2s_config()
259 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), in dw_i2s_config()
260 dev->fifo_th - 1); in dw_i2s_config()
261 i2s_write_reg(dev->i2s_base, TER(ch_reg), TER_TXCHEN | in dw_i2s_config()
262 dev->tdm_mask << TER_TXSLOT_SHIFT); in dw_i2s_config()
264 i2s_write_reg(dev->i2s_base, RCR(ch_reg), in dw_i2s_config()
265 dev->xfer_resolution); in dw_i2s_config()
266 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), in dw_i2s_config()
267 dev->fifo_th - 1); in dw_i2s_config()
268 i2s_write_reg(dev->i2s_base, RER(ch_reg), RER_RXCHEN | in dw_i2s_config()
269 dev->tdm_mask << RER_RXSLOT_SHIFT); in dw_i2s_config()
278 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_hw_params() local
279 struct i2s_clk_config_data *config = &dev->config; in dw_i2s_hw_params()
285 dev->ccr = 0x00; in dw_i2s_hw_params()
286 dev->xfer_resolution = 0x02; in dw_i2s_hw_params()
291 dev->ccr = 0x08; in dw_i2s_hw_params()
292 dev->xfer_resolution = 0x04; in dw_i2s_hw_params()
297 dev->ccr = 0x10; in dw_i2s_hw_params()
298 dev->xfer_resolution = 0x05; in dw_i2s_hw_params()
302 dev_err(dev->dev, "designware-i2s: unsupported PCM fmt"); in dw_i2s_hw_params()
306 if (dev->tdm_slots) in dw_i2s_hw_params()
318 dev_err(dev->dev, "channel not supported\n"); in dw_i2s_hw_params()
322 dw_i2s_config(dev, substream->stream); in dw_i2s_hw_params()
324 i2s_write_reg(dev->i2s_base, CCR, dev->ccr); in dw_i2s_hw_params()
328 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_hw_params()
329 if (dev->i2s_clk_cfg) { in dw_i2s_hw_params()
330 ret = dev->i2s_clk_cfg(config); in dw_i2s_hw_params()
332 dev_err(dev->dev, "runtime audio clk config fail\n"); in dw_i2s_hw_params()
339 ret = clk_set_rate(dev->clk, bitclk); in dw_i2s_hw_params()
341 dev_err(dev->dev, "Can't set I2S clock rate: %d\n", in dw_i2s_hw_params()
353 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_prepare() local
356 i2s_write_reg(dev->i2s_base, TXFFR, 1); in dw_i2s_prepare()
358 i2s_write_reg(dev->i2s_base, RXFFR, 1); in dw_i2s_prepare()
366 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_trigger() local
373 dev->active++; in dw_i2s_trigger()
374 i2s_start(dev, substream); in dw_i2s_trigger()
380 dev->active--; in dw_i2s_trigger()
381 i2s_stop(dev, substream); in dw_i2s_trigger()
392 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); in dw_i2s_set_fmt() local
397 if (dev->capability & DW_I2S_SLAVE) in dw_i2s_set_fmt()
403 if (dev->capability & DW_I2S_MASTER) in dw_i2s_set_fmt()
413 dev_dbg(dev->dev, "dwc : Invalid clock provider format\n"); in dw_i2s_set_fmt()
424 dev->frame_offset = 1; in dw_i2s_set_fmt()
427 dev->frame_offset = 0; in dw_i2s_set_fmt()
430 dev_err(dev->dev, "DAI format unsupported"); in dw_i2s_set_fmt()
440 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai); in dw_i2s_set_tdm_slot() local
454 dev->tdm_slots = slots; in dw_i2s_set_tdm_slot()
455 dev->tdm_mask = rx_mask; in dw_i2s_set_tdm_slot()
457 dev->l_reg = RSLOT_TSLOT(ffs(rx_mask) - 1); in dw_i2s_set_tdm_slot()
458 dev->r_reg = RSLOT_TSLOT(fls(rx_mask) - 1); in dw_i2s_set_tdm_slot()
465 struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); in dw_i2s_dai_probe() local
467 snd_soc_dai_init_dma_data(dai, &dev->play_dma_data, &dev->capture_dma_data); in dw_i2s_dai_probe()
482 static int dw_i2s_runtime_suspend(struct device *dev) in dw_i2s_runtime_suspend() argument
484 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); in dw_i2s_runtime_suspend()
491 static int dw_i2s_runtime_resume(struct device *dev) in dw_i2s_runtime_resume() argument
493 struct dw_i2s_dev *dw_dev = dev_get_drvdata(dev); in dw_i2s_runtime_resume()
506 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); in dw_i2s_suspend() local
508 if (dev->capability & DW_I2S_MASTER) in dw_i2s_suspend()
509 clk_disable(dev->clk); in dw_i2s_suspend()
515 struct dw_i2s_dev *dev = snd_soc_component_get_drvdata(component); in dw_i2s_resume() local
519 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_resume()
520 ret = clk_enable(dev->clk); in dw_i2s_resume()
528 dw_i2s_config(dev, stream); in dw_i2s_resume()
579 static int dw_configure_dai(struct dw_i2s_dev *dev, in dw_configure_dai() argument
587 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); in dw_configure_dai()
588 u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2); in dw_configure_dai()
592 if (dev->capability & DWC_I2S_RECORD && in dw_configure_dai()
593 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) in dw_configure_dai()
596 if (dev->capability & DWC_I2S_PLAY && in dw_configure_dai()
597 dev->quirks & DW_I2S_QUIRK_COMP_PARAM1) in dw_configure_dai()
601 dev_dbg(dev->dev, " designware: play supported\n"); in dw_configure_dai()
605 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) in dw_configure_dai()
615 dev_dbg(dev->dev, "designware: record supported\n"); in dw_configure_dai()
619 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) in dw_configure_dai()
629 dev_dbg(dev->dev, "designware: i2s master mode supported\n"); in dw_configure_dai()
630 dev->capability |= DW_I2S_MASTER; in dw_configure_dai()
632 dev_dbg(dev->dev, "designware: i2s slave mode supported\n"); in dw_configure_dai()
633 dev->capability |= DW_I2S_SLAVE; in dw_configure_dai()
636 dev->fifo_th = fifo_depth / 2; in dw_configure_dai()
640 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, in dw_configure_dai_by_pd() argument
645 u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1); in dw_configure_dai_by_pd()
652 ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates); in dw_configure_dai_by_pd()
656 if (dev->quirks & DW_I2S_QUIRK_16BIT_IDX_OVERRIDE) in dw_configure_dai_by_pd()
659 if (dev->is_jh7110) { in dw_configure_dai_by_pd()
661 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); in dw_configure_dai_by_pd()
666 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; in dw_configure_dai_by_pd()
667 dev->play_dma_data.dt.fifo_size = dev->fifo_th * 2 * in dw_configure_dai_by_pd()
669 dev->play_dma_data.dt.maxburst = 16; in dw_configure_dai_by_pd()
673 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; in dw_configure_dai_by_pd()
674 dev->capture_dma_data.dt.fifo_size = dev->fifo_th * 2 * in dw_configure_dai_by_pd()
676 dev->capture_dma_data.dt.maxburst = 16; in dw_configure_dai_by_pd()
680 dev->play_dma_data.pd.data = pdata->play_dma_data; in dw_configure_dai_by_pd()
681 dev->capture_dma_data.pd.data = pdata->capture_dma_data; in dw_configure_dai_by_pd()
682 dev->play_dma_data.pd.addr = res->start + I2S_TXDMA; in dw_configure_dai_by_pd()
683 dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA; in dw_configure_dai_by_pd()
684 dev->play_dma_data.pd.max_burst = 16; in dw_configure_dai_by_pd()
685 dev->capture_dma_data.pd.max_burst = 16; in dw_configure_dai_by_pd()
686 dev->play_dma_data.pd.addr_width = bus_widths[idx]; in dw_configure_dai_by_pd()
687 dev->capture_dma_data.pd.addr_width = bus_widths[idx]; in dw_configure_dai_by_pd()
688 dev->play_dma_data.pd.filter = pdata->filter; in dw_configure_dai_by_pd()
689 dev->capture_dma_data.pd.filter = pdata->filter; in dw_configure_dai_by_pd()
695 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, in dw_configure_dai_by_dt() argument
699 u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1); in dw_configure_dai_by_dt()
700 u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2); in dw_configure_dai_by_dt()
705 ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000); in dw_configure_dai_by_dt()
712 dev->capability |= DWC_I2S_PLAY; in dw_configure_dai_by_dt()
713 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA; in dw_configure_dai_by_dt()
714 dev->play_dma_data.dt.fifo_size = fifo_depth * in dw_configure_dai_by_dt()
716 dev->play_dma_data.dt.maxburst = 16; in dw_configure_dai_by_dt()
721 dev->capability |= DWC_I2S_RECORD; in dw_configure_dai_by_dt()
722 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA; in dw_configure_dai_by_dt()
723 dev->capture_dma_data.dt.fifo_size = fifo_depth * in dw_configure_dai_by_dt()
725 dev->capture_dma_data.dt.maxburst = 16; in dw_configure_dai_by_dt()
734 static int jh7110_i2s_crg_master_init(struct dw_i2s_dev *dev) in jh7110_i2s_crg_master_init() argument
743 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); in jh7110_i2s_crg_master_init()
752 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); in jh7110_i2s_crg_master_init()
754 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); in jh7110_i2s_crg_master_init()
756 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); in jh7110_i2s_crg_master_init()
790 dev->is_jh7110 = true; in jh7110_i2s_crg_master_init()
804 static int jh7110_i2s_crg_slave_init(struct dw_i2s_dev *dev) in jh7110_i2s_crg_slave_init() argument
817 struct reset_control *resets = devm_reset_control_array_get_exclusive(dev->dev); in jh7110_i2s_crg_slave_init()
830 return dev_err_probe(dev->dev, PTR_ERR(resets), "failed to get i2s resets\n"); in jh7110_i2s_crg_slave_init()
832 ret = clk_bulk_get(dev->dev, ARRAY_SIZE(clks), clks); in jh7110_i2s_crg_slave_init()
834 return dev_err_probe(dev->dev, ret, "failed to get i2s clocks\n"); in jh7110_i2s_crg_slave_init()
878 dev->is_jh7110 = true; in jh7110_i2s_crg_slave_init()
892 static int jh7110_i2srx_crg_init(struct dw_i2s_dev *dev) in jh7110_i2srx_crg_init() argument
897 regmap = syscon_regmap_lookup_by_phandle_args(dev->dev->of_node, in jh7110_i2srx_crg_init()
901 return dev_err_probe(dev->dev, PTR_ERR(regmap), "getting the regmap failed\n"); in jh7110_i2srx_crg_init()
906 return jh7110_i2s_crg_slave_init(dev); in jh7110_i2srx_crg_init()
911 struct dw_i2s_dev *dev = container_of(config, struct dw_i2s_dev, config); in jh7110_i2stx0_clk_cfg() local
914 return clk_set_rate(dev->clk, bclk_rate); in jh7110_i2stx0_clk_cfg()
920 const struct i2s_platform_data *pdata = pdev->dev.platform_data; in dw_i2s_probe()
921 struct dw_i2s_dev *dev; in dw_i2s_probe() local
927 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); in dw_i2s_probe()
928 if (!dev) in dw_i2s_probe()
931 dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL); in dw_i2s_probe()
937 dev->i2s_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in dw_i2s_probe()
938 if (IS_ERR(dev->i2s_base)) in dw_i2s_probe()
939 return PTR_ERR(dev->i2s_base); in dw_i2s_probe()
941 dev->dev = &pdev->dev; in dw_i2s_probe()
942 dev->is_jh7110 = false; in dw_i2s_probe()
945 ret = pdata->i2s_pd_init(dev); in dw_i2s_probe()
951 if (!dev->is_jh7110) { in dw_i2s_probe()
952 dev->reset = devm_reset_control_array_get_optional_shared(&pdev->dev); in dw_i2s_probe()
953 if (IS_ERR(dev->reset)) in dw_i2s_probe()
954 return PTR_ERR(dev->reset); in dw_i2s_probe()
956 ret = reset_control_deassert(dev->reset); in dw_i2s_probe()
963 ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, in dw_i2s_probe()
964 pdev->name, dev); in dw_i2s_probe()
966 dev_err(&pdev->dev, "failed to request irq\n"); in dw_i2s_probe()
971 dev->i2s_reg_comp1 = I2S_COMP_PARAM_1; in dw_i2s_probe()
972 dev->i2s_reg_comp2 = I2S_COMP_PARAM_2; in dw_i2s_probe()
974 dev->capability = pdata->cap; in dw_i2s_probe()
976 dev->quirks = pdata->quirks; in dw_i2s_probe()
977 if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) { in dw_i2s_probe()
978 dev->i2s_reg_comp1 = pdata->i2s_reg_comp1; in dw_i2s_probe()
979 dev->i2s_reg_comp2 = pdata->i2s_reg_comp2; in dw_i2s_probe()
981 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata); in dw_i2s_probe()
984 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); in dw_i2s_probe()
989 if (dev->capability & DW_I2S_MASTER) { in dw_i2s_probe()
991 dev->i2s_clk_cfg = pdata->i2s_clk_cfg; in dw_i2s_probe()
992 if (!dev->i2s_clk_cfg) { in dw_i2s_probe()
993 dev_err(&pdev->dev, "no clock configure method\n"); in dw_i2s_probe()
998 dev->clk = devm_clk_get(&pdev->dev, clk_id); in dw_i2s_probe()
1000 if (IS_ERR(dev->clk)) { in dw_i2s_probe()
1001 ret = PTR_ERR(dev->clk); in dw_i2s_probe()
1005 ret = clk_prepare_enable(dev->clk); in dw_i2s_probe()
1010 dev_set_drvdata(&pdev->dev, dev); in dw_i2s_probe()
1011 ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component, in dw_i2s_probe()
1014 dev_err(&pdev->dev, "not able to register dai\n"); in dw_i2s_probe()
1018 if (!pdata || dev->is_jh7110) { in dw_i2s_probe()
1021 dev->use_pio = true; in dw_i2s_probe()
1022 dev->l_reg = LRBR_LTHR(0); in dw_i2s_probe()
1023 dev->r_reg = RRBR_RTHR(0); in dw_i2s_probe()
1025 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, in dw_i2s_probe()
1027 dev->use_pio = false; in dw_i2s_probe()
1031 dev_err(&pdev->dev, "could not register pcm: %d\n", in dw_i2s_probe()
1037 pm_runtime_enable(&pdev->dev); in dw_i2s_probe()
1041 if (dev->capability & DW_I2S_MASTER) in dw_i2s_probe()
1042 clk_disable_unprepare(dev->clk); in dw_i2s_probe()
1044 reset_control_assert(dev->reset); in dw_i2s_probe()
1050 struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev); in dw_i2s_remove() local
1052 if (dev->capability & DW_I2S_MASTER) in dw_i2s_remove()
1053 clk_disable_unprepare(dev->clk); in dw_i2s_remove()
1055 reset_control_assert(dev->reset); in dw_i2s_remove()
1056 pm_runtime_disable(&pdev->dev); in dw_i2s_remove()