Lines Matching refs:bclk
1282 int lrclk, bclk, mask, base; in wm5100_set_fmt() local
1287 bclk = 0; in wm5100_set_fmt()
1309 bclk |= WM5100_AIF1_BCLK_MSTR; in wm5100_set_fmt()
1313 bclk |= WM5100_AIF1_BCLK_MSTR; in wm5100_set_fmt()
1325 bclk |= WM5100_AIF1_BCLK_INV; in wm5100_set_fmt()
1329 bclk |= WM5100_AIF1_BCLK_INV; in wm5100_set_fmt()
1339 WM5100_AIF1_BCLK_INV, bclk); in wm5100_set_fmt()
1402 int i, base, bclk, aif_rate, lrclk, wl, fl, sr; in wm5100_hw_params() local
1419 bclk = snd_soc_params_to_bclk(params); in wm5100_hw_params()
1420 if (bclk < 0) in wm5100_hw_params()
1421 return bclk; in wm5100_hw_params()
1455 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK"); in wm5100_hw_params()
1463 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0)) in wm5100_hw_params()
1468 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK"); in wm5100_hw_params()
1472 bclk = i; in wm5100_hw_params()
1473 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]); in wm5100_hw_params()
1474 snd_soc_component_update_bits(component, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk); in wm5100_hw_params()
1476 lrclk = bclk_rates[bclk] / params_rate(params); in wm5100_hw_params()
1477 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk); in wm5100_hw_params()