Lines Matching refs:bclk
1557 int lrclk, bclk, fmt_val; in wm2200_set_fmt() local
1560 bclk = 0; in wm2200_set_fmt()
1582 bclk |= WM2200_AIF1_BCLK_MSTR; in wm2200_set_fmt()
1586 bclk |= WM2200_AIF1_BCLK_MSTR; in wm2200_set_fmt()
1598 bclk |= WM2200_AIF1_BCLK_INV; in wm2200_set_fmt()
1602 bclk |= WM2200_AIF1_BCLK_INV; in wm2200_set_fmt()
1612 WM2200_AIF1_BCLK_INV, bclk); in wm2200_set_fmt()
1690 int i, bclk, lrclk, wl, fl, sr_code; in wm2200_hw_params() local
1705 bclk = snd_soc_params_to_bclk(params); in wm2200_hw_params()
1706 if (bclk < 0) in wm2200_hw_params()
1707 return bclk; in wm2200_hw_params()
1725 bclk, wm2200->sysclk); in wm2200_hw_params()
1733 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0)) in wm2200_hw_params()
1738 bclk, wm2200->sysclk); in wm2200_hw_params()
1742 bclk = i; in wm2200_hw_params()
1743 dev_dbg(component->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]); in wm2200_hw_params()
1745 WM2200_AIF1_BCLK_DIV_MASK, bclk); in wm2200_hw_params()
1747 lrclk = bclk_rates[bclk] / params_rate(params); in wm2200_hw_params()
1748 dev_dbg(component->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk); in wm2200_hw_params()