Lines Matching +full:dac +full:- +full:mode +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
21 #include <sound/soc-dapm.h>
50 pll->id = id; in pll_init()
51 mutex_init(&pll->lock); in pll_init()
66 aif->id = id; in aif_init()
85 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; in init_coeff_ram_cache()
90 init_coeff_ram_cache(ram->cache); in coeff_ram_init()
91 mutex_init(&ram->lock); in coeff_ram_init()
101 u8 mask = 0x01 << (aif_id * 2 + !playback); in set_aif_status_active() local
103 status->streams |= mask; in set_aif_status_active()
109 u8 mask = ~(0x01 << (aif_id * 2 + !playback)); in set_aif_status_inactive() local
111 status->streams &= mask; in set_aif_status_inactive()
116 return status->streams; in aifs_active()
121 return (0x03 << aif_id * 2) & status->streams; in aif_active()
282 tscs454->regmap = devm_regmap_init_i2c(i2c, &tscs454_regmap_cfg); in tscs454_data_init()
283 if (IS_ERR(tscs454->regmap)) { in tscs454_data_init()
284 ret = PTR_ERR(tscs454->regmap); in tscs454_data_init()
289 aif_init(&tscs454->aifs[i], i); in tscs454_data_init()
291 mutex_init(&tscs454->aifs_status_lock); in tscs454_data_init()
292 pll_init(&tscs454->pll1, 1); in tscs454_data_init()
293 pll_init(&tscs454->pll2, 2); in tscs454_data_init()
295 coeff_ram_init(&tscs454->dac_ram); in tscs454_data_init()
296 coeff_ram_init(&tscs454->spk_ram); in tscs454_data_init()
297 coeff_ram_init(&tscs454->sub_ram); in tscs454_data_init()
314 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_get()
315 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_get()
319 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_get()
320 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_get()
321 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_get()
322 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_get()
323 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_get()
324 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_get()
325 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_get()
326 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_get()
327 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_get()
329 return -EINVAL; in coeff_ram_get()
334 memcpy(ucontrol->value.bytes.data, in coeff_ram_get()
335 &coeff_ram[ctl->addr * COEFF_SIZE], params->max); in coeff_ram_get()
362 ret = -EIO; in write_coeff_ram()
363 dev_err(component->dev, in write_coeff_ram()
368 ret = regmap_write(tscs454->regmap, r_addr, coeff_addr); in write_coeff_ram()
370 dev_err(component->dev, in write_coeff_ram()
371 "Failed to write dac ram address (%d)\n", ret); in write_coeff_ram()
375 ret = regmap_bulk_write(tscs454->regmap, r_wr, in write_coeff_ram()
379 dev_err(component->dev, in write_coeff_ram()
380 "Failed to write dac ram (%d)\n", ret); in write_coeff_ram()
395 (struct coeff_ram_ctl *)kcontrol->private_value; in coeff_ram_put()
396 struct soc_bytes_ext *params = &ctl->bytes_ext; in coeff_ram_put()
397 unsigned int coeff_cnt = params->max / COEFF_SIZE; in coeff_ram_put()
407 if (strstr(kcontrol->id.name, "DAC")) { in coeff_ram_put()
408 coeff_ram = tscs454->dac_ram.cache; in coeff_ram_put()
409 coeff_ram_lock = &tscs454->dac_ram.lock; in coeff_ram_put()
410 coeff_ram_synced = &tscs454->dac_ram.synced; in coeff_ram_put()
414 } else if (strstr(kcontrol->id.name, "Speaker")) { in coeff_ram_put()
415 coeff_ram = tscs454->spk_ram.cache; in coeff_ram_put()
416 coeff_ram_lock = &tscs454->spk_ram.lock; in coeff_ram_put()
417 coeff_ram_synced = &tscs454->spk_ram.synced; in coeff_ram_put()
421 } else if (strstr(kcontrol->id.name, "Sub")) { in coeff_ram_put()
422 coeff_ram = tscs454->sub_ram.cache; in coeff_ram_put()
423 coeff_ram_lock = &tscs454->sub_ram.lock; in coeff_ram_put()
424 coeff_ram_synced = &tscs454->sub_ram.synced; in coeff_ram_put()
429 return -EINVAL; in coeff_ram_put()
436 memcpy(&coeff_ram[ctl->addr * COEFF_SIZE], in coeff_ram_put()
437 ucontrol->value.bytes.data, params->max); in coeff_ram_put()
439 mutex_lock(&tscs454->pll1.lock); in coeff_ram_put()
440 mutex_lock(&tscs454->pll2.lock); in coeff_ram_put()
446 ctl->addr, coeff_cnt); in coeff_ram_put()
448 dev_err(component->dev, in coeff_ram_put()
457 mutex_unlock(&tscs454->pll2.lock); in coeff_ram_put()
458 mutex_unlock(&tscs454->pll1.lock); in coeff_ram_put()
469 mutex_lock(&tscs454->dac_ram.lock); in coeff_ram_sync()
470 if (!tscs454->dac_ram.synced) { in coeff_ram_sync()
471 ret = write_coeff_ram(component, tscs454->dac_ram.cache, in coeff_ram_sync()
475 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
479 mutex_unlock(&tscs454->dac_ram.lock); in coeff_ram_sync()
481 mutex_lock(&tscs454->spk_ram.lock); in coeff_ram_sync()
482 if (!tscs454->spk_ram.synced) { in coeff_ram_sync()
483 ret = write_coeff_ram(component, tscs454->spk_ram.cache, in coeff_ram_sync()
487 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
491 mutex_unlock(&tscs454->spk_ram.lock); in coeff_ram_sync()
493 mutex_lock(&tscs454->sub_ram.lock); in coeff_ram_sync()
494 if (!tscs454->sub_ram.synced) { in coeff_ram_sync()
495 ret = write_coeff_ram(component, tscs454->sub_ram.cache, in coeff_ram_sync()
499 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
503 mutex_unlock(&tscs454->sub_ram.lock); in coeff_ram_sync()
633 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in set_sysclk()
634 freq = clk_get_rate(tscs454->sysclk); in set_sysclk()
636 freq = tscs454->bclk_freq; in set_sysclk()
639 ret = -EINVAL; in set_sysclk()
640 dev_err(component->dev, in set_sysclk()
647 pll_ctl->settings[i].addr, in set_sysclk()
648 pll_ctl->settings[i].val); in set_sysclk()
650 dev_err(component->dev, in set_sysclk()
662 mutex_lock(&pll->lock); in reserve_pll()
663 pll->users++; in reserve_pll()
664 mutex_unlock(&pll->lock); in reserve_pll()
669 mutex_lock(&pll->lock); in free_pll()
670 pll->users--; in free_pll()
671 mutex_unlock(&pll->lock); in free_pll()
678 snd_soc_dapm_to_component(source->dapm); in pll_connected()
682 if (strstr(source->name, "PLL 1")) { in pll_connected()
683 mutex_lock(&tscs454->pll1.lock); in pll_connected()
684 users = tscs454->pll1.users; in pll_connected()
685 mutex_unlock(&tscs454->pll1.lock); in pll_connected()
686 dev_dbg(component->dev, "%s(): PLL 1 users = %d\n", __func__, in pll_connected()
689 mutex_lock(&tscs454->pll2.lock); in pll_connected()
690 users = tscs454->pll2.users; in pll_connected()
691 mutex_unlock(&tscs454->pll2.lock); in pll_connected()
692 dev_dbg(component->dev, "%s(): PLL 2 users = %d\n", __func__, in pll_connected()
707 snd_soc_dapm_to_component(w->dapm); in pll_power_event()
715 if (strstr(w->name, "PLL 1")) in pll_power_event()
739 dev_err(component->dev, "Failed to %s PLL %d (%d)\n", in pll_power_event()
750 dev_err(component->dev, in pll_power_event()
763 unsigned int mask; in aif_set_provider() local
778 ret = -ENODEV; in aif_set_provider()
779 dev_err(component->dev, "Unknown DAI %d (%d)\n", aif_id, ret); in aif_set_provider()
782 mask = FM_I2SPCTL_PORTMS; in aif_set_provider()
785 ret = snd_soc_component_update_bits(component, reg, mask, val); in aif_set_provider()
787 dev_err(component->dev, "Failed to set DAI %d to %s (%d)\n", in aif_set_provider()
800 ret = aif_set_provider(component, aif->id, aif->provider); in aif_prepare()
812 mutex_lock(&tscs454->aifs_status_lock); in aif_free()
814 dev_dbg(component->dev, "%s(): aif %d\n", __func__, aif->id); in aif_free()
816 set_aif_status_inactive(&tscs454->aifs_status, aif->id, playback); in aif_free()
818 dev_dbg(component->dev, "Set aif %d inactive. Streams status is 0x%x\n", in aif_free()
819 aif->id, tscs454->aifs_status.streams); in aif_free()
821 if (!aif_active(&tscs454->aifs_status, aif->id)) { in aif_free()
822 /* Do config in slave mode */ in aif_free()
823 aif_set_provider(component, aif->id, false); in aif_free()
824 dev_dbg(component->dev, "Freeing pll %d from aif %d\n", in aif_free()
825 aif->pll->id, aif->id); in aif_free()
826 free_pll(aif->pll); in aif_free()
829 if (!aifs_active(&tscs454->aifs_status)) { in aif_free()
830 dev_dbg(component->dev, "Freeing pll %d from ir\n", in aif_free()
831 tscs454->internal_rate.pll->id); in aif_free()
832 free_pll(tscs454->internal_rate.pll); in aif_free()
835 mutex_unlock(&tscs454->aifs_status_lock); in aif_free()
908 "DMic 2", "ClassD", "DAC", "Sub"};
934 SOC_DAPM_ENUM("DAC Mux", dac_mux_enum);
1106 static DECLARE_TLV_DB_SCALE(in_pga_vol_tlv_arr, -1725, 75, 0);
1112 static DECLARE_TLV_DB_MINMAX(in_vol_tlv_arr, -7125, 2400);
1118 static DECLARE_TLV_DB_MINMAX(asrc_vol_tlv_arr, -9562, 600);
1136 static DECLARE_TLV_DB_SCALE(alc_max_gain_tlv_arr, -1200, 600, 0);
1137 static DECLARE_TLV_DB_SCALE(alc_target_tlv_arr, -2850, 150, 0);
1140 static DECLARE_TLV_DB_SCALE(alc_min_gain_tlv_arr, -1725, 600, 0);
1143 static DECLARE_TLV_DB_SCALE(ngth_tlv_arr, -7650, 150, 0);
1192 static DECLARE_TLV_DB_MINMAX(mvol_tlv_arr, -9562, 0);
1196 static DECLARE_TLV_DB_SCALE(hp_vol_tlv_arr, -8850, 75, 0);
1200 static DECLARE_TLV_DB_SCALE(spk_vol_tlv_arr, -7725, 75, 0);
1206 "Pre Scale + EQ Band 0 - 1",
1207 "Pre Scale + EQ Band 0 - 2",
1208 "Pre Scale + EQ Band 0 - 3",
1209 "Pre Scale + EQ Band 0 - 4",
1210 "Pre Scale + EQ Band 0 - 5",
1256 static DECLARE_TLV_DB_MINMAX(mbc_mug_tlv_arr, -4650, 0);
1259 static DECLARE_TLV_DB_MINMAX(thr_tlv_arr, -9562, 0);
1484 (struct coeff_ram_ctl *)kcontrol->private_value; in bytes_info_ext()
1485 struct soc_bytes_ext *params = &ctl->bytes_ext; in bytes_info_ext()
1487 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in bytes_info_ext()
1488 ucontrol->count = params->max; in bytes_info_ext()
1541 SOC_ENUM("DAC Modular Rate", dac_modular_rate_enum),
1572 SOC_ENUM("Manual Mode Plug Type", plug_type_force_enum),
1668 SOC_ENUM("ALC Mode", alc_mode_enum),
1708 SOC_ENUM("DAC Polarity Left", dac_pol_r_enum),
1709 SOC_ENUM("DAC Polarity Right", dac_pol_l_enum),
1710 SOC_ENUM("DAC Dither", dac_dith_enum),
1711 SOC_SINGLE("DAC Mute Switch", R_DACCTL, FB_DACCTL_DACMUTE, 1, 0),
1712 SOC_SINGLE("DAC De-Emphasis Switch", R_DACCTL, FB_DACCTL_DACDEM, 1, 0),
1717 SOC_SINGLE("Speaker De-Emphasis Switch",
1722 SOC_SINGLE("Sub De-Emphasis Switch", R_SUBCTL, FB_SUBCTL_SUBDEM, 1, 0),
1725 SOC_SINGLE("DAC DC Removal Switch", R_DCCTL, FB_DCCTL_DACDCBYP, 1, 1),
1764 SOC_ENUM("Speaker MBC 3 Mode", spk_mbc3_lvl_det_mode_enum),
1766 SOC_ENUM("Speaker MBC 2 Mode", spk_mbc2_lvl_det_mode_enum),
1768 SOC_ENUM("Speaker MBC 1 Mode", spk_mbc1_lvl_det_mode_enum),
1772 SOC_SINGLE_TLV("Speaker MBC1 Make-Up Gain Volume", R_SPKMBCMUG1,
1789 SOC_SINGLE_TLV("Speaker MBC2 Make-Up Gain Volume", R_SPKMBCMUG2,
1806 SOC_SINGLE_TLV("Speaker MBC 3 Make-Up Gain Volume", R_SPKMBCMUG3,
1822 SOC_ENUM("Speaker CLE Level Mode", spk_cle_lvl_mode_enum),
1831 SOC_SINGLE_TLV("Speaker CLE Make-Up Gain Volume", R_SPKCLEMUG,
1883 SOC_SINGLE("DAC EQ 2 Switch",
1885 SOC_ENUM("DAC EQ 2 Band", dac_eq_enums[0]),
1886 SOC_SINGLE("DAC EQ 1 Switch", R_DACEQFILT, FB_DACEQFILT_EQ1EN, 1, 0),
1887 SOC_ENUM("DAC EQ 1 Band", dac_eq_enums[1]),
1889 SOC_SINGLE("DAC MBC 3 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN3, 1, 0),
1890 SOC_SINGLE("DAC MBC 2 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN2, 1, 0),
1891 SOC_SINGLE("DAC MBC 1 Switch", R_DACMBCEN, FB_DACMBCEN_MBCEN1, 1, 0),
1893 SOC_ENUM("DAC MBC 3 Mode", dac_mbc3_lvl_det_mode_enum),
1894 SOC_ENUM("DAC MBC 3 Window", dac_mbc3_win_sel_enum),
1895 SOC_ENUM("DAC MBC 2 Mode", dac_mbc2_lvl_det_mode_enum),
1896 SOC_ENUM("DAC MBC 2 Window", dac_mbc2_win_sel_enum),
1897 SOC_ENUM("DAC MBC 1 Mode", dac_mbc1_lvl_det_mode_enum),
1898 SOC_ENUM("DAC MBC 1 Window", dac_mbc1_win_sel_enum),
1900 SOC_ENUM("DAC MBC 1 Phase Polarity", dac_mbc1_phase_pol_enum),
1901 SOC_SINGLE_TLV("DAC MBC 1 Make-Up Gain Volume", R_DACMBCMUG1,
1905 SOC_SINGLE_TLV("DAC MBC 1 Compressor Threshold Volume", R_DACMBCTHR1,
1909 SOC_ENUM("DAC MBC 1 Compressor Ratio", dac_mbc1_comp_rat_enum),
1912 SND_SOC_BYTES("DAC MBC 1 Attack", R_DACMBCATK1L, 2),
1915 SND_SOC_BYTES("DAC MBC 1 Release", R_DACMBCREL1L, 2),
1917 SOC_ENUM("DAC MBC 2 Phase Polarity", dac_mbc2_phase_pol_enum),
1918 SOC_SINGLE_TLV("DAC MBC 2 Make-Up Gain Volume", R_DACMBCMUG2,
1922 SOC_SINGLE_TLV("DAC MBC 2 Compressor Threshold Volume", R_DACMBCTHR2,
1926 SOC_ENUM("DAC MBC 2 Compressor Ratio", dac_mbc2_comp_rat_enum),
1929 SND_SOC_BYTES("DAC MBC 2 Attack", R_DACMBCATK2L, 2),
1932 SND_SOC_BYTES("DAC MBC 2 Release", R_DACMBCREL2L, 2),
1934 SOC_ENUM("DAC MBC 3 Phase Polarity", dac_mbc3_phase_pol_enum),
1935 SOC_SINGLE_TLV("DAC MBC 3 Make-Up Gain Volume", R_DACMBCMUG3,
1939 SOC_SINGLE_TLV("DAC MBC 3 Threshold Volume", R_DACMBCTHR3,
1943 SOC_ENUM("DAC MBC 3 Compressor Ratio", dac_mbc3_comp_rat_enum),
1946 SND_SOC_BYTES("DAC MBC 3 Attack", R_DACMBCATK3L, 3),
1949 SND_SOC_BYTES("DAC MBC 3 Release", R_DACMBCREL3L, 3),
1951 SOC_ENUM("DAC CLE Level Mode", dac_cle_lvl_mode_enum),
1952 SOC_ENUM("DAC CLE Window", dac_cle_win_sel_enum),
1953 SOC_SINGLE("DAC CLE Expander Switch",
1955 SOC_SINGLE("DAC CLE Limiter Switch",
1957 SOC_SINGLE("DAC CLE Compressor Switch",
1960 SOC_SINGLE_TLV("DAC CLE Make-Up Gain Volume", R_DACCLEMUG,
1964 SOC_SINGLE_TLV("DAC Compressor Threshold Volume", R_DACCOMPTHR,
1968 SOC_ENUM("DAC Compressor Ratio", dac_comp_rat_enum),
1971 SND_SOC_BYTES("DAC Compressor Attack", R_DACCOMPATKL, 2),
1974 SND_SOC_BYTES("DAC Compressor Release", R_DACCOMPRELL, 2),
1976 SOC_SINGLE_TLV("DAC Limiter Threshold Volume", R_DACLIMTHR,
1980 SOC_SINGLE_TLV("DAC Limiter Target Volume", R_DACLIMTGT,
1985 SND_SOC_BYTES("DAC Limiter Attack", R_DACLIMATKL, 2),
1988 SND_SOC_BYTES("DAC Limiter Release", R_DACLIMRELL, 2),
1990 SOC_SINGLE_TLV("DAC Expander Threshold Volume", R_DACEXPTHR,
1994 SOC_ENUM("DAC Expander Ratio", dac_exp_rat_enum),
1997 SND_SOC_BYTES("DAC Expander Attack", R_DACEXPATKL, 2),
2000 SND_SOC_BYTES("DAC Expander Release", R_DACEXPRELL, 2),
2002 SOC_SINGLE("DAC 3D Switch", R_DACFXCTL, FB_DACFXCTL_3DEN, 1, 0),
2003 SOC_SINGLE("DAC Treble Enhancement Switch",
2005 SOC_SINGLE("DAC Treble NLF Switch",
2007 SOC_SINGLE("DAC Bass Enhancement Switch",
2009 SOC_SINGLE("DAC Bass NLF Switch",
2022 SOC_ENUM("Sub MBC 3 Mode", sub_mbc3_lvl_det_mode_enum),
2024 SOC_ENUM("Sub MBC 2 Mode", sub_mbc2_lvl_det_mode_enum),
2026 SOC_ENUM("Sub MBC 1 Mode", sub_mbc1_lvl_det_mode_enum),
2030 SOC_SINGLE_TLV("Sub MBC 1 Make-Up Gain Volume", R_SUBMBCMUG1,
2047 SOC_SINGLE_TLV("Sub MBC 2 Make-Up Gain Volume", R_SUBMBCMUG2,
2064 SOC_SINGLE_TLV("Sub MBC 3 Make-Up Gain Volume", R_SUBMBCMUG3,
2080 SOC_ENUM("Sub CLE Level Mode", sub_cle_lvl_mode_enum),
2089 SOC_SINGLE_TLV("Sub CLE Make-Up Gain Volume", R_SUBCLEMUG,
2139 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 1", BIQUAD_SIZE, 0x00),
2140 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 2", BIQUAD_SIZE, 0x05),
2141 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 3", BIQUAD_SIZE, 0x0a),
2142 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 4", BIQUAD_SIZE, 0x0f),
2143 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 5", BIQUAD_SIZE, 0x14),
2144 COEFF_RAM_CTL("DAC Cascade 1 Left BiQuad 6", BIQUAD_SIZE, 0x19),
2146 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 1", BIQUAD_SIZE, 0x20),
2147 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 2", BIQUAD_SIZE, 0x25),
2148 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 3", BIQUAD_SIZE, 0x2a),
2149 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 4", BIQUAD_SIZE, 0x2f),
2150 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 5", BIQUAD_SIZE, 0x34),
2151 COEFF_RAM_CTL("DAC Cascade 1 Right BiQuad 6", BIQUAD_SIZE, 0x39),
2153 COEFF_RAM_CTL("DAC Cascade 1 Left Prescale", COEFF_SIZE, 0x1f),
2154 COEFF_RAM_CTL("DAC Cascade 1 Right Prescale", COEFF_SIZE, 0x3f),
2156 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 1", BIQUAD_SIZE, 0x40),
2157 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 2", BIQUAD_SIZE, 0x45),
2158 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 3", BIQUAD_SIZE, 0x4a),
2159 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 4", BIQUAD_SIZE, 0x4f),
2160 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 5", BIQUAD_SIZE, 0x54),
2161 COEFF_RAM_CTL("DAC Cascade 2 Left BiQuad 6", BIQUAD_SIZE, 0x59),
2163 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 1", BIQUAD_SIZE, 0x60),
2164 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 2", BIQUAD_SIZE, 0x65),
2165 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 3", BIQUAD_SIZE, 0x6a),
2166 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 4", BIQUAD_SIZE, 0x6f),
2167 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 5", BIQUAD_SIZE, 0x74),
2168 COEFF_RAM_CTL("DAC Cascade 2 Right BiQuad 6", BIQUAD_SIZE, 0x79),
2170 COEFF_RAM_CTL("DAC Cascade 2 Left Prescale", COEFF_SIZE, 0x5f),
2171 COEFF_RAM_CTL("DAC Cascade 2 Right Prescale", COEFF_SIZE, 0x7f),
2173 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 1", BIQUAD_SIZE, 0x80),
2174 COEFF_RAM_CTL("DAC Bass Extraction BiQuad 2", BIQUAD_SIZE, 0x85),
2176 COEFF_RAM_CTL("DAC Bass Non Linear Function 1", COEFF_SIZE, 0x8a),
2177 COEFF_RAM_CTL("DAC Bass Non Linear Function 2", COEFF_SIZE, 0x8b),
2179 COEFF_RAM_CTL("DAC Bass Limiter BiQuad", BIQUAD_SIZE, 0x8c),
2181 COEFF_RAM_CTL("DAC Bass Cut Off BiQuad", BIQUAD_SIZE, 0x91),
2183 COEFF_RAM_CTL("DAC Bass Mix", COEFF_SIZE, 0x96),
2185 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 1", BIQUAD_SIZE, 0x97),
2186 COEFF_RAM_CTL("DAC Treb Extraction BiQuad 2", BIQUAD_SIZE, 0x9c),
2188 COEFF_RAM_CTL("DAC Treb Non Linear Function 1", COEFF_SIZE, 0xa1),
2189 COEFF_RAM_CTL("DAC Treb Non Linear Function 2", COEFF_SIZE, 0xa2),
2191 COEFF_RAM_CTL("DAC Treb Limiter BiQuad", BIQUAD_SIZE, 0xa3),
2193 COEFF_RAM_CTL("DAC Treb Cut Off BiQuad", BIQUAD_SIZE, 0xa8),
2195 COEFF_RAM_CTL("DAC Treb Mix", COEFF_SIZE, 0xad),
2197 COEFF_RAM_CTL("DAC 3D", COEFF_SIZE, 0xae),
2199 COEFF_RAM_CTL("DAC 3D Mix", COEFF_SIZE, 0xaf),
2201 COEFF_RAM_CTL("DAC MBC 1 BiQuad 1", BIQUAD_SIZE, 0xb0),
2202 COEFF_RAM_CTL("DAC MBC 1 BiQuad 2", BIQUAD_SIZE, 0xb5),
2204 COEFF_RAM_CTL("DAC MBC 2 BiQuad 1", BIQUAD_SIZE, 0xba),
2205 COEFF_RAM_CTL("DAC MBC 2 BiQuad 2", BIQUAD_SIZE, 0xbf),
2207 COEFF_RAM_CTL("DAC MBC 3 BiQuad 1", BIQUAD_SIZE, 0xc4),
2208 COEFF_RAM_CTL("DAC MBC 3 BiQuad 2", BIQUAD_SIZE, 0xc9),
2415 SND_SOC_DAPM_DAC("DAC Left", NULL, R_PWRM4, FB_PWRM4_OPDACLPU, 0),
2416 SND_SOC_DAPM_DAC("DAC Right", NULL, R_PWRM4, FB_PWRM4_OPDACRPU, 0),
2425 SND_SOC_DAPM_MUX("DAC Mux", SND_SOC_NOPM, 0, 0,
2517 /* DAC Path */
2518 {"DAC Mux", "CH 4_5", "CH 4_5 Mux"},
2519 {"DAC Mux", "CH 2_3", "CH 2_3 Mux"},
2520 {"DAC Mux", "CH 0_1", "CH 0_1 Mux"},
2521 {"DAC Left", NULL, "DAC Mux"},
2522 {"DAC Right", NULL, "DAC Mux"},
2523 {"DAC Left", NULL, "PLLs"},
2524 {"DAC Right", NULL, "PLLs"},
2527 {"Headphone Left", NULL, "DAC Left"},
2528 {"Headphone Right", NULL, "DAC Right"},
2532 {"Line Out Left", NULL, "DAC Left"},
2533 {"Line Out Right", NULL, "DAC Right"},
2636 struct snd_soc_component *component = dai->component; in tscs454_set_sysclk()
2641 dev_dbg(component->dev, "%s(): freq = %u\n", __func__, freq); in tscs454_set_sysclk()
2646 if (bclk_dai != dai->id) in tscs454_set_sysclk()
2649 tscs454->bclk_freq = freq; in tscs454_set_sysclk()
2656 unsigned int mask; in tscs454_set_bclk_ratio() local
2658 struct snd_soc_component *component = dai->component; in tscs454_set_bclk_ratio()
2662 dev_dbg(component->dev, "set_bclk_ratio() id = %d ratio = %u\n", in tscs454_set_bclk_ratio()
2663 dai->id, ratio); in tscs454_set_bclk_ratio()
2665 switch (dai->id) { in tscs454_set_bclk_ratio()
2667 mask = FM_I2SCMC_BCMP1; in tscs454_set_bclk_ratio()
2671 mask = FM_I2SCMC_BCMP2; in tscs454_set_bclk_ratio()
2675 mask = FM_I2SCMC_BCMP3; in tscs454_set_bclk_ratio()
2679 ret = -EINVAL; in tscs454_set_bclk_ratio()
2680 dev_err(component->dev, "Unknown audio interface (%d)\n", ret); in tscs454_set_bclk_ratio()
2695 ret = -EINVAL; in tscs454_set_bclk_ratio()
2696 dev_err(component->dev, "Unsupported bclk ratio (%d)\n", ret); in tscs454_set_bclk_ratio()
2701 R_I2SCMC, mask, val << shift); in tscs454_set_bclk_ratio()
2703 dev_err(component->dev, in tscs454_set_bclk_ratio()
2718 aif->provider = true; in set_aif_provider_from_fmt()
2721 aif->provider = false; in set_aif_provider_from_fmt()
2724 ret = -EINVAL; in set_aif_provider_from_fmt()
2725 dev_err(component->dev, "Unsupported format (%d)\n", ret); in set_aif_provider_from_fmt()
2749 ret = -EINVAL; in set_aif_tdm_delay()
2750 dev_err(component->dev, in set_aif_tdm_delay()
2757 dev_err(component->dev, "Failed to setup tdm format (%d)\n", in set_aif_tdm_delay()
2783 ret = -EINVAL; in set_aif_format_from_fmt()
2784 dev_err(component->dev, in set_aif_format_from_fmt()
2812 ret = -EINVAL; in set_aif_format_from_fmt()
2813 dev_err(component->dev, "Format unsupported (%d)\n", ret); in set_aif_format_from_fmt()
2820 dev_err(component->dev, "Failed to set DAI %d format (%d)\n", in set_aif_format_from_fmt()
2847 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2848 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2867 ret = -EINVAL; in set_aif_clock_format_from_fmt()
2868 dev_err(component->dev, "Format unknown (%d)\n", ret); in set_aif_clock_format_from_fmt()
2875 dev_err(component->dev, in set_aif_clock_format_from_fmt()
2886 struct snd_soc_component *component = dai->component; in tscs454_set_dai_fmt()
2888 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_set_dai_fmt()
2895 ret = set_aif_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2899 ret = set_aif_clock_format_from_fmt(component, dai->id, fmt); in tscs454_set_dai_fmt()
2910 struct snd_soc_component *component = dai->component; in tscs454_dai1_set_tdm_slot()
2918 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2919 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2934 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2935 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2950 ret = -EINVAL; in tscs454_dai1_set_tdm_slot()
2951 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2956 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai1_set_tdm_slot()
2967 struct snd_soc_component *component = dai->component; in tscs454_dai23_set_tdm_slot()
2976 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2977 dev_err(component->dev, "Invalid TDM slot mask (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
2981 switch (dai->id) { in tscs454_dai23_set_tdm_slot()
2989 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
2990 dev_err(component->dev, "Unrecognized interface %d (%d)\n", in tscs454_dai23_set_tdm_slot()
2991 dai->id, ret); in tscs454_dai23_set_tdm_slot()
3003 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
3004 dev_err(component->dev, "Invalid number of slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3019 ret = -EINVAL; in tscs454_dai23_set_tdm_slot()
3020 dev_err(component->dev, "Invalid TDM slot width (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3025 dev_err(component->dev, "Failed to set slots (%d)\n", ret); in tscs454_dai23_set_tdm_slot()
3083 ret = -EINVAL; in set_aif_fs()
3084 dev_err(component->dev, "Unsupported sample rate (%d)\n", ret); in set_aif_fs()
3099 ret = -EINVAL; in set_aif_fs()
3100 dev_err(component->dev, "DAI ID not recognized (%d)\n", ret); in set_aif_fs()
3107 dev_err(component->dev, in set_aif_fs()
3137 ret = -EINVAL; in set_aif_sample_format()
3138 dev_err(component->dev, "Unsupported format width (%d)\n", ret); in set_aif_sample_format()
3153 ret = -EINVAL; in set_aif_sample_format()
3154 dev_err(component->dev, "AIF ID not recognized (%d)\n", ret); in set_aif_sample_format()
3161 dev_err(component->dev, in set_aif_sample_format()
3173 struct snd_soc_component *component = dai->component; in tscs454_hw_params()
3176 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_params()
3180 mutex_lock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3182 dev_dbg(component->dev, "%s(): aif %d fs = %u\n", __func__, in tscs454_hw_params()
3183 aif->id, fs); in tscs454_hw_params()
3185 if (!aif_active(&tscs454->aifs_status, aif->id)) { in tscs454_hw_params()
3187 aif->pll = &tscs454->pll1; in tscs454_hw_params()
3189 aif->pll = &tscs454->pll2; in tscs454_hw_params()
3191 dev_dbg(component->dev, "Reserving pll %d for aif %d\n", in tscs454_hw_params()
3192 aif->pll->id, aif->id); in tscs454_hw_params()
3194 reserve_pll(aif->pll); in tscs454_hw_params()
3197 if (!aifs_active(&tscs454->aifs_status)) { /* First active aif */ in tscs454_hw_params()
3200 tscs454->internal_rate.pll = &tscs454->pll1; in tscs454_hw_params()
3202 tscs454->internal_rate.pll = &tscs454->pll2; in tscs454_hw_params()
3204 dev_dbg(component->dev, "Reserving pll %d for ir\n", in tscs454_hw_params()
3205 tscs454->internal_rate.pll->id); in tscs454_hw_params()
3207 reserve_pll(tscs454->internal_rate.pll); in tscs454_hw_params()
3210 ret = set_aif_fs(component, aif->id, fs); in tscs454_hw_params()
3212 dev_err(component->dev, "Failed to set aif fs (%d)\n", ret); in tscs454_hw_params()
3216 ret = set_aif_sample_format(component, params_format(params), aif->id); in tscs454_hw_params()
3218 dev_err(component->dev, in tscs454_hw_params()
3223 set_aif_status_active(&tscs454->aifs_status, aif->id, in tscs454_hw_params()
3224 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_params()
3226 dev_dbg(component->dev, "Set aif %d active. Streams status is 0x%x\n", in tscs454_hw_params()
3227 aif->id, tscs454->aifs_status.streams); in tscs454_hw_params()
3231 mutex_unlock(&tscs454->aifs_status_lock); in tscs454_hw_params()
3239 struct snd_soc_component *component = dai->component; in tscs454_hw_free()
3241 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_hw_free()
3244 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); in tscs454_hw_free()
3251 struct snd_soc_component *component = dai->component; in tscs454_prepare()
3253 struct aif *aif = &tscs454->aifs[dai->id]; in tscs454_prepare()
3288 switch (tscs454->sysclk_src_id) { in tscs454_probe()
3302 ret = -EINVAL; in tscs454_probe()
3303 dev_err(component->dev, "Invalid sysclk src id (%d)\n", ret); in tscs454_probe()
3310 dev_err(component->dev, "Failed to set PLL input (%d)\n", ret); in tscs454_probe()
3314 if (tscs454->sysclk_src_id < PLL_INPUT_BCLK) in tscs454_probe()
3339 .name = "tscs454-dai1",
3359 .name = "tscs454-dai2",
3379 .name = "tscs454-dai3",
3409 tscs454 = devm_kzalloc(&i2c->dev, sizeof(*tscs454), GFP_KERNEL); in tscs454_i2c_probe()
3411 return -ENOMEM; in tscs454_i2c_probe()
3420 tscs454->sysclk = devm_clk_get(&i2c->dev, src_names[src]); in tscs454_i2c_probe()
3421 if (!IS_ERR(tscs454->sysclk)) { in tscs454_i2c_probe()
3423 } else if (PTR_ERR(tscs454->sysclk) != -ENOENT) { in tscs454_i2c_probe()
3424 ret = PTR_ERR(tscs454->sysclk); in tscs454_i2c_probe()
3425 dev_err(&i2c->dev, "Failed to get sysclk (%d)\n", ret); in tscs454_i2c_probe()
3429 dev_dbg(&i2c->dev, "PLL input is %s\n", src_names[src]); in tscs454_i2c_probe()
3430 tscs454->sysclk_src_id = src; in tscs454_i2c_probe()
3432 ret = regmap_write(tscs454->regmap, in tscs454_i2c_probe()
3435 dev_err(&i2c->dev, "Failed to reset the component (%d)\n", ret); in tscs454_i2c_probe()
3438 regcache_mark_dirty(tscs454->regmap); in tscs454_i2c_probe()
3440 ret = regmap_register_patch(tscs454->regmap, tscs454_patch, in tscs454_i2c_probe()
3443 dev_err(&i2c->dev, "Failed to apply patch (%d)\n", ret); in tscs454_i2c_probe()
3447 regmap_write(tscs454->regmap, R_PAGESEL, 0x00); in tscs454_i2c_probe()
3449 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_tscs454, in tscs454_i2c_probe()
3452 dev_err(&i2c->dev, "Failed to register component (%d)\n", ret); in tscs454_i2c_probe()