Lines Matching refs:RV
115 #define RV(v, b) ((v)<<(b)) macro
136 #define RV_HPVOLL_P6DB RV(FV_HPVOLL_P6DB, FB_HPVOLL)
137 #define RV_HPVOLL_N88PT5DB RV(FV_HPVOLL_N88PT5DB, FB_HPVOLL)
138 #define RV_HPVOLL_MUTE RV(FV_HPVOLL_MUTE, FB_HPVOLL)
159 #define RV_HPVOLR_P6DB RV(FV_HPVOLR_P6DB, FB_HPVOLR)
160 #define RV_HPVOLR_N88PT5DB RV(FV_HPVOLR_N88PT5DB, FB_HPVOLR)
161 #define RV_HPVOLR_MUTE RV(FV_HPVOLR_MUTE, FB_HPVOLR)
182 #define RV_SPKVOLL_P12DB RV(FV_SPKVOLL_P12DB, FB_SPKVOLL)
184 RV(FV_SPKVOLL_N77PT25DB, FB_SPKVOLL)
186 #define RV_SPKVOLL_MUTE RV(FV_SPKVOLL_MUTE, FB_SPKVOLL)
207 #define RV_SPKVOLR_P12DB RV(FV_SPKVOLR_P12DB, FB_SPKVOLR)
209 RV(FV_SPKVOLR_N77PT25DB, FB_SPKVOLR)
211 #define RV_SPKVOLR_MUTE RV(FV_SPKVOLR_MUTE, FB_SPKVOLR)
232 #define RV_DACVOLL_0DB RV(FV_DACVOLL_0DB, FB_DACVOLL)
234 RV(FV_DACVOLL_N95PT625DB, FB_DACVOLL)
236 #define RV_DACVOLL_MUTE RV(FV_DACVOLL_MUTE, FB_DACVOLL)
257 #define RV_DACVOLR_0DB RV(FV_DACVOLR_0DB, FB_DACVOLR)
259 RV(FV_DACVOLR_N95PT625DB, FB_DACVOLR)
261 #define RV_DACVOLR_MUTE RV(FV_DACVOLR_MUTE, FB_DACVOLR)
282 #define RV_ADCVOLL_P24DB RV(FV_ADCVOLL_P24DB, FB_ADCVOLL)
284 RV(FV_ADCVOLL_N71PT25DB, FB_ADCVOLL)
286 #define RV_ADCVOLL_MUTE RV(FV_ADCVOLL_MUTE, FB_ADCVOLL)
307 #define RV_ADCVOLR_P24DB RV(FV_ADCVOLR_P24DB, FB_ADCVOLR)
309 RV(FV_ADCVOLR_N71PT25DB, FB_ADCVOLR)
311 #define RV_ADCVOLR_MUTE RV(FV_ADCVOLR_MUTE, FB_ADCVOLR)
344 RV(FV_INVOLL_INMUTEL_ENABLE, FB_INVOLL_INMUTEL)
347 RV(FV_INVOLL_INMUTEL_DISABLE, FB_INVOLL_INMUTEL)
350 RV(FV_INVOLL_IZCL_ENABLE, FB_INVOLL_IZCL)
353 RV(FV_INVOLL_IZCL_DISABLE, FB_INVOLL_IZCL)
355 #define RV_INVOLL_P30DB RV(FV_INVOLL_P30DB, FB_INVOLL)
356 #define RV_INVOLL_N17PT25DB RV(FV_INVOLL_N17PT25DB, FB_INVOLL)
389 RV(FV_INVOLR_INMUTER_ENABLE, FB_INVOLR_INMUTER)
392 RV(FV_INVOLR_INMUTER_DISABLE, FB_INVOLR_INMUTER)
395 RV(FV_INVOLR_IZCR_ENABLE, FB_INVOLR_IZCR)
398 RV(FV_INVOLR_IZCR_DISABLE, FB_INVOLR_IZCR)
400 #define RV_INVOLR_P30DB RV(FV_INVOLR_P30DB, FB_INVOLR)
401 #define RV_INVOLR_N17PT25DB RV(FV_INVOLR_N17PT25DB, FB_INVOLR)
422 RV(FV_INMODE_DS_LRIN1, FB_INMODE_DS)
425 RV(FV_INMODE_DS_LRIN2, FB_INMODE_DS)
457 #define RV_INSELL_IN1 RV(FV_INSELL_IN1, FB_INSELL)
458 #define RV_INSELL_IN2 RV(FV_INSELL_IN2, FB_INSELL)
459 #define RV_INSELL_IN3 RV(FV_INSELL_IN3, FB_INSELL)
460 #define RV_INSELL_D2S RV(FV_INSELL_D2S, FB_INSELL)
462 RV(FV_INSELL_MICBSTL_OFF, FB_INSELL_MICBSTL)
465 RV(FV_INSELL_MICBSTL_10DB, FB_INSELL_MICBSTL)
468 RV(FV_INSELL_MICBSTL_20DB, FB_INSELL_MICBSTL)
471 RV(FV_INSELL_MICBSTL_30DB, FB_INSELL_MICBSTL)
503 #define RV_INSELR_IN1 RV(FV_INSELR_IN1, FB_INSELR)
504 #define RV_INSELR_IN2 RV(FV_INSELR_IN2, FB_INSELR)
505 #define RV_INSELR_IN3 RV(FV_INSELR_IN3, FB_INSELR)
506 #define RV_INSELR_D2S RV(FV_INSELR_D2S, FB_INSELR)
508 RV(FV_INSELR_MICBSTR_OFF, FB_INSELR_MICBSTR)
511 RV(FV_INSELR_MICBSTR_10DB, FB_INSELR_MICBSTR)
514 RV(FV_INSELR_MICBSTR_20DB, FB_INSELR_MICBSTR)
517 RV(FV_INSELR_MICBSTR_30DB, FB_INSELR_MICBSTR)
564 RV(FV_AIC1_BCLKINV_ENABLE, FB_AIC1_BCLKINV)
567 RV(FV_AIC1_BCLKINV_DISABLE, FB_AIC1_BCLKINV)
569 #define RV_AIC1_MS_MASTER RV(FV_AIC1_MS_MASTER, FB_AIC1_MS)
570 #define RV_AIC1_MS_SLAVE RV(FV_AIC1_MS_SLAVE, FB_AIC1_MS)
572 RV(FV_AIC1_LRP_INVERT, FB_AIC1_LRP)
575 RV(FV_AIC1_LRP_NORMAL, FB_AIC1_LRP)
577 #define RV_AIC1_WL_16 RV(FV_AIC1_WL_16, FB_AIC1_WL)
578 #define RV_AIC1_WL_20 RV(FV_AIC1_WL_20, FB_AIC1_WL)
579 #define RV_AIC1_WL_24 RV(FV_AIC1_WL_24, FB_AIC1_WL)
580 #define RV_AIC1_WL_32 RV(FV_AIC1_WL_32, FB_AIC1_WL)
582 RV(FV_AIC1_FORMAT_RIGHT, FB_AIC1_FORMAT)
585 RV(FV_AIC1_FORMAT_LEFT, FB_AIC1_FORMAT)
588 RV(FV_AIC1_FORMAT_I2S, FB_AIC1_FORMAT)
622 RV(FV_AIC2_BLRCM_DAC_BCLK_LRCLK_SHARED, FB_AIC2_BLRCM)
684 RV(FV_CNVRTR0_ADCPOLR_INVERT, FB_CNVRTR0_ADCPOLR)
687 RV(FV_CNVRTR0_ADCPOLR_NORMAL, FB_CNVRTR0_ADCPOLR)
690 RV(FV_CNVRTR0_ADCPOLL_INVERT, FB_CNVRTR0_ADCPOLL)
693 RV(FV_CNVRTR0_ADCPOLL_NORMAL, FB_CNVRTR0_ADCPOLL)
696 RV(FV_CNVRTR0_ADCMU_ENABLE, FB_CNVRTR0_ADCMU)
699 RV(FV_CNVRTR0_ADCMU_DISABLE, FB_CNVRTR0_ADCMU)
702 RV(FV_CNVRTR0_ADCHPDR_ENABLE, FB_CNVRTR0_ADCHPDR)
705 RV(FV_CNVRTR0_ADCHPDR_DISABLE, FB_CNVRTR0_ADCHPDR)
708 RV(FV_CNVRTR0_ADCHPDL_ENABLE, FB_CNVRTR0_ADCHPDL)
711 RV(FV_CNVRTR0_ADCHPDL_DISABLE, FB_CNVRTR0_ADCHPDL)
748 RV(FV_ADCSR_ABCM_AUTO, FB_ADCSR_ABCM)
751 RV(FV_ADCSR_ABCM_32, FB_ADCSR_ABCM)
754 RV(FV_ADCSR_ABCM_40, FB_ADCSR_ABCM)
757 RV(FV_ADCSR_ABCM_64, FB_ADCSR_ABCM)
759 #define RV_ADCSR_ABR_32 RV(FV_ADCSR_ABR_32, FB_ADCSR_ABR)
761 RV(FV_ADCSR_ABR_44_1, FB_ADCSR_ABR)
763 #define RV_ADCSR_ABR_48 RV(FV_ADCSR_ABR_48, FB_ADCSR_ABR)
764 #define RV_ADCSR_ABR_ RV(FV_ADCSR_ABR_, FB_ADCSR_ABR)
766 RV(FV_ADCSR_ABM_PT25, FB_ADCSR_ABM)
768 #define RV_ADCSR_ABM_PT5 RV(FV_ADCSR_ABM_PT5, FB_ADCSR_ABM)
769 #define RV_ADCSR_ABM_1 RV(FV_ADCSR_ABM_1, FB_ADCSR_ABM)
770 #define RV_ADCSR_ABM_2 RV(FV_ADCSR_ABM_2, FB_ADCSR_ABM)
824 RV(FV_CNVRTR1_DACPOLR_INVERT, FB_CNVRTR1_DACPOLR)
827 RV(FV_CNVRTR1_DACPOLR_NORMAL, FB_CNVRTR1_DACPOLR)
830 RV(FV_CNVRTR1_DACPOLL_INVERT, FB_CNVRTR1_DACPOLL)
833 RV(FV_CNVRTR1_DACPOLL_NORMAL, FB_CNVRTR1_DACPOLL)
836 RV(FV_CNVRTR1_DMONOMIX_ENABLE, FB_CNVRTR1_DMONOMIX)
839 RV(FV_CNVRTR1_DMONOMIX_DISABLE, FB_CNVRTR1_DMONOMIX)
842 RV(FV_CNVRTR1_DACMU_ENABLE, FB_CNVRTR1_DACMU)
845 RV(FV_CNVRTR1_DACMU_DISABLE, FB_CNVRTR1_DACMU)
882 RV(FV_DACSR_DBCM_AUTO, FB_DACSR_DBCM)
885 RV(FV_DACSR_DBCM_32, FB_DACSR_DBCM)
888 RV(FV_DACSR_DBCM_40, FB_DACSR_DBCM)
891 RV(FV_DACSR_DBCM_64, FB_DACSR_DBCM)
893 #define RV_DACSR_DBR_32 RV(FV_DACSR_DBR_32, FB_DACSR_DBR)
895 RV(FV_DACSR_DBR_44_1, FB_DACSR_DBR)
897 #define RV_DACSR_DBR_48 RV(FV_DACSR_DBR_48, FB_DACSR_DBR)
899 RV(FV_DACSR_DBM_PT25, FB_DACSR_DBM)
901 #define RV_DACSR_DBM_PT5 RV(FV_DACSR_DBM_PT5, FB_DACSR_DBM)
902 #define RV_DACSR_DBM_1 RV(FV_DACSR_DBM_1, FB_DACSR_DBM)
903 #define RV_DACSR_DBM_2 RV(FV_DACSR_DBM_2, FB_DACSR_DBM)
961 RV(FV_PWRM1_BSTL_ENABLE, FB_PWRM1_BSTL)
964 RV(FV_PWRM1_BSTL_DISABLE, FB_PWRM1_BSTL)
967 RV(FV_PWRM1_BSTR_ENABLE, FB_PWRM1_BSTR)
970 RV(FV_PWRM1_BSTR_DISABLE, FB_PWRM1_BSTR)
973 RV(FV_PWRM1_PGAL_ENABLE, FB_PWRM1_PGAL)
976 RV(FV_PWRM1_PGAL_DISABLE, FB_PWRM1_PGAL)
979 RV(FV_PWRM1_PGAR_ENABLE, FB_PWRM1_PGAR)
982 RV(FV_PWRM1_PGAR_DISABLE, FB_PWRM1_PGAR)
985 RV(FV_PWRM1_ADCL_ENABLE, FB_PWRM1_ADCL)
988 RV(FV_PWRM1_ADCL_DISABLE, FB_PWRM1_ADCL)
991 RV(FV_PWRM1_ADCR_ENABLE, FB_PWRM1_ADCR)
994 RV(FV_PWRM1_ADCR_DISABLE, FB_PWRM1_ADCR)
997 RV(FV_PWRM1_MICB_ENABLE, FB_PWRM1_MICB)
1000 RV(FV_PWRM1_MICB_DISABLE, FB_PWRM1_MICB)
1003 RV(FV_PWRM1_DIGENB_DISABLE, FB_PWRM1_DIGENB)
1006 RV(FV_PWRM1_DIGENB_ENABLE, FB_PWRM1_DIGENB)
1067 RV(FV_PWRM2_D2S_ENABLE, FB_PWRM2_D2S)
1070 RV(FV_PWRM2_D2S_DISABLE, FB_PWRM2_D2S)
1073 RV(FV_PWRM2_HPL_ENABLE, FB_PWRM2_HPL)
1076 RV(FV_PWRM2_HPL_DISABLE, FB_PWRM2_HPL)
1079 RV(FV_PWRM2_HPR_ENABLE, FB_PWRM2_HPR)
1082 RV(FV_PWRM2_HPR_DISABLE, FB_PWRM2_HPR)
1085 RV(FV_PWRM2_SPKL_ENABLE, FB_PWRM2_SPKL)
1088 RV(FV_PWRM2_SPKL_DISABLE, FB_PWRM2_SPKL)
1091 RV(FV_PWRM2_SPKR_ENABLE, FB_PWRM2_SPKR)
1094 RV(FV_PWRM2_SPKR_DISABLE, FB_PWRM2_SPKR)
1097 RV(FV_PWRM2_INSELL_ENABLE, FB_PWRM2_INSELL)
1100 RV(FV_PWRM2_INSELL_DISABLE, FB_PWRM2_INSELL)
1103 RV(FV_PWRM2_INSELR_ENABLE, FB_PWRM2_INSELR)
1106 RV(FV_PWRM2_INSELR_DISABLE, FB_PWRM2_INSELR)
1109 RV(FV_PWRM2_VREF_ENABLE, FB_PWRM2_VREF)
1112 RV(FV_PWRM2_VREF_DISABLE, FB_PWRM2_VREF)
1166 RV(FV_CONFIG0_ASDM_HALF, FB_CONFIG0_ASDM)
1169 RV(FV_CONFIG0_ASDM_FULL, FB_CONFIG0_ASDM)
1172 RV(FV_CONFIG0_ASDM_AUTO, FB_CONFIG0_ASDM)
1175 RV(FV_CONFIG0_DSDM_HALF, FB_CONFIG0_DSDM)
1178 RV(FV_CONFIG0_DSDM_FULL, FB_CONFIG0_DSDM)
1181 RV(FV_CONFIG0_DSDM_AUTO, FB_CONFIG0_DSDM)
1184 RV(FV_CONFIG0_DC_BYPASS_ENABLE, FB_CONFIG0_DC_BYPASS)
1187 RV(FV_CONFIG0_DC_BYPASS_DISABLE, FB_CONFIG0_DC_BYPASS)
1190 RV(FV_CONFIG0_SD_FORCE_ON_ENABLE, FB_CONFIG0_SD_FORCE_ON)
1193 RV(FV_CONFIG0_SD_FORCE_ON_DISABLE, FB_CONFIG0_SD_FORCE_ON)
1248 RV(FV_CONFIG1_EQ2_EN_ENABLE, FB_CONFIG1_EQ2_EN)
1251 RV(FV_CONFIG1_EQ2_EN_DISABLE, FB_CONFIG1_EQ2_EN)
1254 RV(FV_CONFIG1_EQ2_BE_PRE, FB_CONFIG1_EQ2_BE)
1257 RV(FV_CONFIG1_EQ2_BE_PRE_EQ_0, FB_CONFIG1_EQ2_BE)
1260 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_1, FB_CONFIG1_EQ2_BE)
1263 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_2, FB_CONFIG1_EQ2_BE)
1266 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_3, FB_CONFIG1_EQ2_BE)
1269 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_4, FB_CONFIG1_EQ2_BE)
1272 RV(FV_CONFIG1_EQ2_BE_PRE_EQ0_5, FB_CONFIG1_EQ2_BE)
1275 RV(FV_CONFIG1_EQ1_EN_ENABLE, FB_CONFIG1_EQ1_EN)
1278 RV(FV_CONFIG1_EQ1_EN_DISABLE, FB_CONFIG1_EQ1_EN)
1281 RV(FV_CONFIG1_EQ1_BE_PRE, FB_CONFIG1_EQ1_BE)
1284 RV(FV_CONFIG1_EQ1_BE_PRE_EQ_0, FB_CONFIG1_EQ1_BE)
1287 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_1, FB_CONFIG1_EQ1_BE)
1290 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_2, FB_CONFIG1_EQ1_BE)
1293 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_3, FB_CONFIG1_EQ1_BE)
1296 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_4, FB_CONFIG1_EQ1_BE)
1299 RV(FV_CONFIG1_EQ1_BE_PRE_EQ0_5, FB_CONFIG1_EQ1_BE)
1340 RV(FV_DMICCTL_DMICEN_ENABLE, FB_DMICCTL_DMICEN)
1343 RV(FV_DMICCTL_DMICEN_DISABLE, FB_DMICCTL_DMICEN)
1346 RV(FV_DMICCTL_DMONO_STEREO, FB_DMICCTL_DMONO)
1349 RV(FV_DMICCTL_DMONO_MONO, FB_DMICCTL_DMONO)
1401 RV(FV_CLECTL_LVL_MODE_AVG, FB_CLECTL_LVL_MODE)
1404 RV(FV_CLECTL_LVL_MODE_PEAK, FB_CLECTL_LVL_MODE)
1407 RV(FV_CLECTL_WINDOWSEL_512, FB_CLECTL_WINDOWSEL)
1410 RV(FV_CLECTL_WINDOWSEL_64, FB_CLECTL_WINDOWSEL)
1413 RV(FV_CLECTL_EXP_EN_ENABLE, FB_CLECTL_EXP_EN)
1416 RV(FV_CLECTL_EXP_EN_DISABLE, FB_CLECTL_EXP_EN)
1419 RV(FV_CLECTL_LIMIT_EN_ENABLE, FB_CLECTL_LIMIT_EN)
1422 RV(FV_CLECTL_LIMIT_EN_DISABLE, FB_CLECTL_LIMIT_EN)
1425 RV(FV_CLECTL_COMP_EN_ENABLE, FB_CLECTL_COMP_EN)
1428 RV(FV_CLECTL_COMP_EN_DISABLE, FB_CLECTL_COMP_EN)
1452 RV(FV_MUGAIN_CLEMUG_46PT5DB, FB_MUGAIN_CLEMUG)
1455 RV(FV_MUGAIN_CLEMUG_0DB, FB_MUGAIN_CLEMUG)
1476 #define RV_COMPTH_0DB RV(FV_COMPTH_0DB, FB_COMPTH)
1478 RV(FV_COMPTH_N95PT625DB, FB_COMPTH)
1564 #define RV_LIMTH_0DB RV(FV_LIMTH_0DB, FB_LIMTH)
1565 #define RV_LIMTH_N95PT625DB RV(FV_LIMTH_N95PT625DB, FB_LIMTH)
1585 #define RV_LIMTGT_0DB RV(FV_LIMTGT_0DB, FB_LIMTGT)
1587 RV(FV_LIMTGT_N95PT625DB, FB_LIMTGT)
1660 #define RV_EXPTH_0DB RV(FV_EXPTH_0DB, FB_EXPTH)
1661 #define RV_EXPTH_N95PT625DB RV(FV_EXPTH_N95PT625DB, FB_EXPTH)
1771 RV(FV_FXCTL_3DEN_ENABLE, FB_FXCTL_3DEN)
1774 RV(FV_FXCTL_3DEN_DISABLE, FB_FXCTL_3DEN)
1777 RV(FV_FXCTL_TEEN_ENABLE, FB_FXCTL_TEEN)
1780 RV(FV_FXCTL_TEEN_DISABLE, FB_FXCTL_TEEN)
1783 RV(FV_FXCTL_TNLFBYPASS_ENABLE, FB_FXCTL_TNLFBYPASS)
1786 RV(FV_FXCTL_TNLFBYPASS_DISABLE, FB_FXCTL_TNLFBYPASS)
1789 RV(FV_FXCTL_BEEN_ENABLE, FB_FXCTL_BEEN)
1792 RV(FV_FXCTL_BEEN_DISABLE, FB_FXCTL_BEEN)
1795 RV(FV_FXCTL_BNLFBYPASS_ENABLE, FB_FXCTL_BNLFBYPASS)
1798 RV(FV_FXCTL_BNLFBYPASS_DISABLE, FB_FXCTL_BNLFBYPASS)
1927 RV(FV_DCOFSEL_DC_COEF_SEL_2_N8, FB_DCOFSEL_DC_COEF_SEL)
1930 RV(FV_DCOFSEL_DC_COEF_SEL_2_N9, FB_DCOFSEL_DC_COEF_SEL)
1933 RV(FV_DCOFSEL_DC_COEF_SEL_2_N10, FB_DCOFSEL_DC_COEF_SEL)
1936 RV(FV_DCOFSEL_DC_COEF_SEL_2_N11, FB_DCOFSEL_DC_COEF_SEL)
1939 RV(FV_DCOFSEL_DC_COEF_SEL_2_N12, FB_DCOFSEL_DC_COEF_SEL)
1942 RV(FV_DCOFSEL_DC_COEF_SEL_2_N13, FB_DCOFSEL_DC_COEF_SEL)
1945 RV(FV_DCOFSEL_DC_COEF_SEL_2_N14, FB_DCOFSEL_DC_COEF_SEL)
1948 RV(FV_DCOFSEL_DC_COEF_SEL_2_N15, FB_DCOFSEL_DC_COEF_SEL)
2159 RV(FV_PLLCTL1C_PDB_PLL2_ENABLE, FB_PLLCTL1C_PDB_PLL2)
2162 RV(FV_PLLCTL1C_PDB_PLL2_DISABLE, FB_PLLCTL1C_PDB_PLL2)
2165 RV(FV_PLLCTL1C_PDB_PLL1_ENABLE, FB_PLLCTL1C_PDB_PLL1)
2168 RV(FV_PLLCTL1C_PDB_PLL1_DISABLE, FB_PLLCTL1C_PDB_PLL1)
2229 #define RV_RESET_ENABLE RV(FV_RESET_ENABLE, FB_RESET)
2294 RV(FV_PLLREFSEL_PLL2_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL2_REF_SEL)
2297 RV(FV_PLLREFSEL_PLL2_REF_SEL_MCLK2, FB_PLLREFSEL_PLL2_REF_SEL)
2300 RV(FV_PLLREFSEL_PLL1_REF_SEL_XTAL_MCLK1, FB_PLLREFSEL_PLL1_REF_SEL)
2303 RV(FV_PLLREFSEL_PLL1_REF_SEL_MCLK2, FB_PLLREFSEL_PLL1_REF_SEL)