soc/codecs/tlv320aic31xx.h

42 #define AIC31XX_REG(page, reg)	((page * 128) + reg)  macro
44 #define AIC31XX_PAGECTL		AIC31XX_REG(0, 0) /* Page Control Register */
47 #define AIC31XX_RESET		AIC31XX_REG(0, 1) /* Software reset register */
48 #define AIC31XX_OT_FLAG		AIC31XX_REG(0, 3) /* OT FLAG register */
49 #define AIC31XX_CLKMUX		AIC31XX_REG(0, 4) /* Clock clock Gen muxing, Multiplexers*/
50 #define AIC31XX_PLLPR		AIC31XX_REG(0, 5) /* PLL P and R-VAL register */
51 #define AIC31XX_PLLJ		AIC31XX_REG(0, 6) /* PLL J-VAL register */
52 #define AIC31XX_PLLDMSB		AIC31XX_REG(0, 7) /* PLL D-VAL MSB register */
53 #define AIC31XX_PLLDLSB		AIC31XX_REG(0, 8) /* PLL D-VAL LSB register */
54 #define AIC31XX_NDAC		AIC31XX_REG(0, 11) /* DAC NDAC_VAL register*/
55 #define AIC31XX_MDAC		AIC31XX_REG(0, 12) /* DAC MDAC_VAL register */
56 #define AIC31XX_DOSRMSB		AIC31XX_REG(0, 13) /* DAC OSR setting register 1, MSB value */
57 #define AIC31XX_DOSRLSB		AIC31XX_REG(0, 14) /* DAC OSR setting register 2, LSB value */
58 #define AIC31XX_MINI_DSP_INPOL	AIC31XX_REG(0, 16)
59 #define AIC31XX_NADC		AIC31XX_REG(0, 18) /* Clock setting register 8, PLL */
60 #define AIC31XX_MADC		AIC31XX_REG(0, 19) /* Clock setting register 9, PLL */
61 #define AIC31XX_AOSR		AIC31XX_REG(0, 20) /* ADC Oversampling (AOSR) Register */
62 #define AIC31XX_CLKOUTMUX	AIC31XX_REG(0, 25) /* Clock setting register 9, Multiplexers */
63 #define AIC31XX_CLKOUTMVAL	AIC31XX_REG(0, 26) /* Clock setting register 10, CLOCKOUT M divider valu…
64 #define AIC31XX_IFACE1		AIC31XX_REG(0, 27) /* Audio Interface Setting Register 1 */
65 #define AIC31XX_DATA_OFFSET	AIC31XX_REG(0, 28) /* Audio Data Slot Offset Programming */
66 #define AIC31XX_IFACE2		AIC31XX_REG(0, 29) /* Audio Interface Setting Register 2 */
67 #define AIC31XX_BCLKN		AIC31XX_REG(0, 30) /* Clock setting register 11, BCLK N Divider */
68 #define AIC31XX_IFACESEC1	AIC31XX_REG(0, 31) /* Audio Interface Setting Register 3, Secondary Audio…
69 #define AIC31XX_IFACESEC2	AIC31XX_REG(0, 32) /* Audio Interface Setting Register 4 */
70 #define AIC31XX_IFACESEC3	AIC31XX_REG(0, 33) /* Audio Interface Setting Register 5 */
71 #define AIC31XX_I2C		AIC31XX_REG(0, 34) /* I2C Bus Condition */
72 #define AIC31XX_ADCFLAG		AIC31XX_REG(0, 36) /* ADC FLAG */
73 #define AIC31XX_DACFLAG1	AIC31XX_REG(0, 37) /* DAC Flag Registers */
74 #define AIC31XX_DACFLAG2	AIC31XX_REG(0, 38)
75 #define AIC31XX_OFFLAG		AIC31XX_REG(0, 39) /* Sticky Interrupt flag (overflow) */
76 #define AIC31XX_INTRDACFLAG	AIC31XX_REG(0, 44) /* Sticy DAC Interrupt flags */
77 #define AIC31XX_INTRADCFLAG	AIC31XX_REG(0, 45) /* Sticy ADC Interrupt flags */
78 #define AIC31XX_INTRDACFLAG2	AIC31XX_REG(0, 46) /* DAC Interrupt flags 2 */
79 #define AIC31XX_INTRADCFLAG2	AIC31XX_REG(0, 47) /* ADC Interrupt flags 2 */
80 #define AIC31XX_INT1CTRL	AIC31XX_REG(0, 48) /* INT1 interrupt control */
81 #define AIC31XX_INT2CTRL	AIC31XX_REG(0, 49) /* INT2 interrupt control */
82 #define AIC31XX_GPIO1		AIC31XX_REG(0, 51) /* GPIO1 control */
83 #define AIC31XX_DACPRB		AIC31XX_REG(0, 60)
84 #define AIC31XX_ADCPRB		AIC31XX_REG(0, 61) /* ADC Instruction Set Register */
85 #define AIC31XX_DACSETUP	AIC31XX_REG(0, 63) /* DAC channel setup register */
86 #define AIC31XX_DACMUTE		AIC31XX_REG(0, 64) /* DAC Mute and volume control register */
87 #define AIC31XX_LDACVOL		AIC31XX_REG(0, 65) /* Left DAC channel digital volume control */
88 #define AIC31XX_RDACVOL		AIC31XX_REG(0, 66) /* Right DAC channel digital volume control */
89 #define AIC31XX_HSDETECT	AIC31XX_REG(0, 67) /* Headset detection */
90 #define AIC31XX_ADCSETUP	AIC31XX_REG(0, 81) /* ADC Digital Mic */
91 #define AIC31XX_ADCFGA		AIC31XX_REG(0, 82) /* ADC Digital Volume Control Fine Adjust */
92 #define AIC31XX_ADCVOL		AIC31XX_REG(0, 83) /* ADC Digital Volume Control Coarse Adjust */
95 #define AIC31XX_HPDRIVER	AIC31XX_REG(1, 31) /* Headphone drivers */
96 #define AIC31XX_SPKAMP		AIC31XX_REG(1, 32) /* Class-D Speakear Amplifier */
97 #define AIC31XX_HPPOP		AIC31XX_REG(1, 33) /* HP Output Drivers POP Removal Settings */
98 #define AIC31XX_SPPGARAMP	AIC31XX_REG(1, 34) /* Output Driver PGA Ramp-Down Period Control */
99 #define AIC31XX_DACMIXERROUTE	AIC31XX_REG(1, 35) /* DAC_L and DAC_R Output Mixer Routing */
100 #define AIC31XX_LANALOGHPL	AIC31XX_REG(1, 36) /* Left Analog Vol to HPL */
101 #define AIC31XX_RANALOGHPR	AIC31XX_REG(1, 37) /* Right Analog Vol to HPR */
102 #define AIC31XX_LANALOGSPL	AIC31XX_REG(1, 38) /* Left Analog Vol to SPL */
103 #define AIC31XX_RANALOGSPR	AIC31XX_REG(1, 39) /* Right Analog Vol to SPR */
104 #define AIC31XX_HPLGAIN		AIC31XX_REG(1, 40) /* HPL Driver */
105 #define AIC31XX_HPRGAIN		AIC31XX_REG(1, 41) /* HPR Driver */
106 #define AIC31XX_SPLGAIN		AIC31XX_REG(1, 42) /* SPL Driver */
107 #define AIC31XX_SPRGAIN		AIC31XX_REG(1, 43) /* SPR Driver */
108 #define AIC31XX_HPCONTROL	AIC31XX_REG(1, 44) /* HP Driver Control */
109 #define AIC31XX_MICBIAS		AIC31XX_REG(1, 46) /* MIC Bias Control */
110 #define AIC31XX_MICPGA		AIC31XX_REG(1, 47) /* MIC PGA*/
111 #define AIC31XX_MICPGAPI	AIC31XX_REG(1, 48) /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selecti…
112 #define AIC31XX_MICPGAMI	AIC31XX_REG(1, 49) /* ADC Input Selection for M-Terminal */
113 #define AIC31XX_MICPGACM	AIC31XX_REG(1, 50) /* Input CM Settings */