soc/codecs/tlv320adcx140.c

1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
41 	"ti,gpo-config-1",
42 	"ti,gpo-config-2",
43 	"ti,gpo-config-3",
44 	"ti,gpo-config-4",
163 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
164 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
166 /* ADC gain. From 0 to 42 dB in 1 dB steps */
169 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
170 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
174 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
175 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
180 	"Linear Phase", "Low Latency", "Ultra-low Latency"
316 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
318 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
320 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
322 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
324 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
326 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
328 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
330 	SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
333 	SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
335 	SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
337 	SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
339 	SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
342 	SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
421 	SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
499 	{"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
606 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;  in adcx140_phase_calib_info()
607 	uinfo->count = 1;  in adcx140_phase_calib_info()
608 	uinfo->value.integer.min = 0;  in adcx140_phase_calib_info()
609 	uinfo->value.integer.max = 1;  in adcx140_phase_calib_info()
620 	value->value.integer.value[0] = adcx140->phase_calib_on ? 1 : 0;  in adcx140_phase_calib_get()
633 	bool v = value->value.integer.value[0] ? true : false;  in adcx140_phase_calib_put()
635 	if (adcx140->phase_calib_on != v) {  in adcx140_phase_calib_put()
636 		adcx140->phase_calib_on = v;  in adcx140_phase_calib_put()
637 		return 1;  in adcx140_phase_calib_put()
685 	if (adcx140->gpio_reset) {  in adcx140_reset()
686 		gpiod_direction_output(adcx140->gpio_reset, 0);  in adcx140_reset()
687 		/* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */  in adcx140_reset()
689 		gpiod_direction_output(adcx140->gpio_reset, 1);  in adcx140_reset()
691 		ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,  in adcx140_reset()
705 	struct snd_soc_component *component = adcx140->component;  in adcx140_pwr_ctrl()
710 	if (adcx140->micbias_vg && power_state)  in adcx140_pwr_ctrl()
714 		ret = regmap_write(adcx140->regmap, ADCX140_PHASE_CALIB,  in adcx140_pwr_ctrl()
715 			adcx140->phase_calib_on ? 0x00 : 0x40);  in adcx140_pwr_ctrl()
717 			dev_err(component->dev, "%s: register write error %d\n",  in adcx140_pwr_ctrl()
721 	regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,  in adcx140_pwr_ctrl()
729 	struct snd_soc_component *component = dai->component;  in adcx140_hw_params()
747 		dev_err(component->dev, "%s: Unsupported width %d\n",  in adcx140_hw_params()
749 		return -EINVAL;  in adcx140_hw_params()
765 	struct snd_soc_component *component = codec_dai->component;  in adcx140_set_dai_fmt()
780 		dev_err(component->dev, "Invalid DAI clock provider\n");  in adcx140_set_dai_fmt()
781 		return -EINVAL;  in adcx140_set_dai_fmt()
793 		offset = 1;  in adcx140_set_dai_fmt()
800 		dev_err(component->dev, "Invalid DAI interface format\n");  in adcx140_set_dai_fmt()
801 		return -EINVAL;  in adcx140_set_dai_fmt()
816 		dev_err(component->dev, "Invalid DAI clock signal polarity\n");  in adcx140_set_dai_fmt()
817 		return -EINVAL;  in adcx140_set_dai_fmt()
823 	adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;  in adcx140_set_dai_fmt()
848 	struct snd_soc_component *component = codec_dai->component;  in adcx140_set_dai_tdm_slot()
856 		dev_err(component->dev, "Only lower adjacent slots are supported\n");  in adcx140_set_dai_tdm_slot()
857 		return -EINVAL;  in adcx140_set_dai_tdm_slot()
867 		dev_err(component->dev, "Unsupported slot width %d\n", slot_width);  in adcx140_set_dai_tdm_slot()
868 		return -EINVAL;  in adcx140_set_dai_tdm_slot()
871 	adcx140->slot_width = slot_width;  in adcx140_set_dai_tdm_slot()
890 		ret = device_property_read_u32_array(adcx140->dev,  in adcx140_configure_gpo()
898 			dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);  in adcx140_configure_gpo()
899 			return -EINVAL;  in adcx140_configure_gpo()
902 		if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {  in adcx140_configure_gpo()
903 			dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);  in adcx140_configure_gpo()
904 			return -EINVAL;  in adcx140_configure_gpo()
908 				 gpo_outputs[1];  in adcx140_configure_gpo()
909 		ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,  in adcx140_configure_gpo()
926 	gpio_count = device_property_count_u32(adcx140->dev,  in adcx140_configure_gpio()
927 			"ti,gpio-config");  in adcx140_configure_gpio()
932 		return -EINVAL;  in adcx140_configure_gpio()
934 	ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",  in adcx140_configure_gpio()
940 		dev_err(adcx140->dev, "GPIO config out of range\n");  in adcx140_configure_gpio()
941 		return -EINVAL;  in adcx140_configure_gpio()
944 	if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {  in adcx140_configure_gpio()
945 		dev_err(adcx140->dev, "GPIO drive out of range\n");  in adcx140_configure_gpio()
946 		return -EINVAL;  in adcx140_configure_gpio()
950 		| gpio_outputs[1];  in adcx140_configure_gpio()
952 	return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);  in adcx140_configure_gpio()
972 	ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",  in adcx140_codec_probe()
976 		adcx140->micbias_vg = false;  in adcx140_codec_probe()
978 		adcx140->micbias_vg = true;  in adcx140_codec_probe()
981 	ret = device_property_read_u32(adcx140->dev, "ti,vref-source",  in adcx140_codec_probe()
987 		dev_err(adcx140->dev, "Mic Bias source value is invalid\n");  in adcx140_codec_probe()
988 		return -EINVAL;  in adcx140_codec_probe()
997 	if (adcx140->supply_areg == NULL)  in adcx140_codec_probe()
1000 	ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);  in adcx140_codec_probe()
1002 		dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);  in adcx140_codec_probe()
1006 	/* 8.4.3: Wait >= 1ms after entering active mode. */  in adcx140_codec_probe()
1009 	pdm_count = device_property_count_u32(adcx140->dev,  in adcx140_codec_probe()
1010 					      "ti,pdm-edge-select");  in adcx140_codec_probe()
1012 		ret = device_property_read_u32_array(adcx140->dev,  in adcx140_codec_probe()
1013 						     "ti,pdm-edge-select",  in adcx140_codec_probe()
1019 			pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);  in adcx140_codec_probe()
1021 		ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,  in adcx140_codec_probe()
1027 	gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");  in adcx140_codec_probe()
1029 		ret = device_property_read_u32_array(adcx140->dev,  in adcx140_codec_probe()
1030 						     "ti,gpi-config",  in adcx140_codec_probe()
1038 		ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,  in adcx140_codec_probe()
1046 		ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,  in adcx140_codec_probe()
1060 	ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,  in adcx140_codec_probe()
1064 		dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);  in adcx140_codec_probe()
1066 	tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");  in adcx140_codec_probe()
1068 		ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,  in adcx140_codec_probe()
1071 			dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);  in adcx140_codec_probe()
1109 	.suspend_bias_off	= 1,
1111 	.use_pmdown_time	= 1,
1112 	.endianness		= 1,
1117 		.name = "tlv320adcx140-codec",
1126 		.symmetric_rate = 1,
1144 	regulator_disable(adcx140->supply_areg);  in adcx140_disable_regulator()
1152 	adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);  in adcx140_i2c_probe()
1154 		return -ENOMEM;  in adcx140_i2c_probe()
1156 	adcx140->phase_calib_on = false;  in adcx140_i2c_probe()
1157 	adcx140->dev = &i2c->dev;  in adcx140_i2c_probe()
1159 	adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,  in adcx140_i2c_probe()
1161 	if (IS_ERR(adcx140->gpio_reset))  in adcx140_i2c_probe()
1162 		dev_info(&i2c->dev, "Reset GPIO not defined\n");  in adcx140_i2c_probe()
1164 	adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,  in adcx140_i2c_probe()
1166 	if (IS_ERR(adcx140->supply_areg)) {  in adcx140_i2c_probe()
1167 		if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)  in adcx140_i2c_probe()
1168 			return -EPROBE_DEFER;  in adcx140_i2c_probe()
1170 		adcx140->supply_areg = NULL;  in adcx140_i2c_probe()
1172 		ret = regulator_enable(adcx140->supply_areg);  in adcx140_i2c_probe()
1174 			dev_err(adcx140->dev, "Failed to enable areg\n");  in adcx140_i2c_probe()
1178 		ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);  in adcx140_i2c_probe()
1183 	adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);  in adcx140_i2c_probe()
1184 	if (IS_ERR(adcx140->regmap)) {  in adcx140_i2c_probe()
1185 		ret = PTR_ERR(adcx140->regmap);  in adcx140_i2c_probe()
1186 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",  in adcx140_i2c_probe()
1193 	return devm_snd_soc_register_component(&i2c->dev,  in adcx140_i2c_probe()
1195 					       adcx140_dai_driver, 1);  in adcx140_i2c_probe()
1200 	{ "tlv320adc5140", 1 },
1208 		.name	= "tlv320adcx140-codec",