Lines Matching refs:ADC3XXX_REG
69 #define ADC3XXX_REG(page, reg) ((page * ADC3XXX_PAGE_SIZE) + reg) macro
75 #define ADC3XXX_PAGE_SELECT ADC3XXX_REG(0, 0)
76 #define ADC3XXX_RESET ADC3XXX_REG(0, 1)
80 #define ADC3XXX_CLKGEN_MUX ADC3XXX_REG(0, 4)
81 #define ADC3XXX_PLL_PROG_PR ADC3XXX_REG(0, 5)
82 #define ADC3XXX_PLL_PROG_J ADC3XXX_REG(0, 6)
83 #define ADC3XXX_PLL_PROG_D_MSB ADC3XXX_REG(0, 7)
84 #define ADC3XXX_PLL_PROG_D_LSB ADC3XXX_REG(0, 8)
88 #define ADC3XXX_ADC_NADC ADC3XXX_REG(0, 18)
89 #define ADC3XXX_ADC_MADC ADC3XXX_REG(0, 19)
90 #define ADC3XXX_ADC_AOSR ADC3XXX_REG(0, 20)
91 #define ADC3XXX_ADC_IADC ADC3XXX_REG(0, 21)
95 #define ADC3XXX_CLKOUT_MUX ADC3XXX_REG(0, 25)
96 #define ADC3XXX_CLKOUT_M_DIV ADC3XXX_REG(0, 26)
97 #define ADC3XXX_INTERFACE_CTRL_1 ADC3XXX_REG(0, 27)
98 #define ADC3XXX_CH_OFFSET_1 ADC3XXX_REG(0, 28)
99 #define ADC3XXX_INTERFACE_CTRL_2 ADC3XXX_REG(0, 29)
100 #define ADC3XXX_BCLK_N_DIV ADC3XXX_REG(0, 30)
101 #define ADC3XXX_INTERFACE_CTRL_3 ADC3XXX_REG(0, 31)
102 #define ADC3XXX_INTERFACE_CTRL_4 ADC3XXX_REG(0, 32)
103 #define ADC3XXX_INTERFACE_CTRL_5 ADC3XXX_REG(0, 33)
104 #define ADC3XXX_I2S_SYNC ADC3XXX_REG(0, 34)
106 #define ADC3XXX_ADC_FLAG ADC3XXX_REG(0, 36)
107 #define ADC3XXX_CH_OFFSET_2 ADC3XXX_REG(0, 37)
108 #define ADC3XXX_I2S_TDM_CTRL ADC3XXX_REG(0, 38)
110 #define ADC3XXX_INTR_FLAG_1 ADC3XXX_REG(0, 42)
111 #define ADC3XXX_INTR_FLAG_2 ADC3XXX_REG(0, 43)
113 #define ADC3XXX_INTR_FLAG_ADC1 ADC3XXX_REG(0, 45)
115 #define ADC3XXX_INTR_FLAG_ADC2 ADC3XXX_REG(0, 47)
116 #define ADC3XXX_INT1_CTRL ADC3XXX_REG(0, 48)
117 #define ADC3XXX_INT2_CTRL ADC3XXX_REG(0, 49)
119 #define ADC3XXX_GPIO2_CTRL ADC3XXX_REG(0, 51)
120 #define ADC3XXX_GPIO1_CTRL ADC3XXX_REG(0, 52)
121 #define ADC3XXX_DOUT_CTRL ADC3XXX_REG(0, 53)
123 #define ADC3XXX_SYNC_CTRL_1 ADC3XXX_REG(0, 57)
124 #define ADC3XXX_SYNC_CTRL_2 ADC3XXX_REG(0, 58)
125 #define ADC3XXX_CIC_GAIN_CTRL ADC3XXX_REG(0, 59)
127 #define ADC3XXX_PRB_SELECT ADC3XXX_REG(0, 61)
128 #define ADC3XXX_INST_MODE_CTRL ADC3XXX_REG(0, 62)
130 #define ADC3XXX_MIC_POLARITY_CTRL ADC3XXX_REG(0, 80)
131 #define ADC3XXX_ADC_DIGITAL ADC3XXX_REG(0, 81)
132 #define ADC3XXX_ADC_FGA ADC3XXX_REG(0, 82)
133 #define ADC3XXX_LADC_VOL ADC3XXX_REG(0, 83)
134 #define ADC3XXX_RADC_VOL ADC3XXX_REG(0, 84)
135 #define ADC3XXX_ADC_PHASE_COMP ADC3XXX_REG(0, 85)
136 #define ADC3XXX_LEFT_CHN_AGC_1 ADC3XXX_REG(0, 86)
137 #define ADC3XXX_LEFT_CHN_AGC_2 ADC3XXX_REG(0, 87)
138 #define ADC3XXX_LEFT_CHN_AGC_3 ADC3XXX_REG(0, 88)
139 #define ADC3XXX_LEFT_CHN_AGC_4 ADC3XXX_REG(0, 89)
140 #define ADC3XXX_LEFT_CHN_AGC_5 ADC3XXX_REG(0, 90)
141 #define ADC3XXX_LEFT_CHN_AGC_6 ADC3XXX_REG(0, 91)
142 #define ADC3XXX_LEFT_CHN_AGC_7 ADC3XXX_REG(0, 92)
143 #define ADC3XXX_LEFT_AGC_GAIN ADC3XXX_REG(0, 93)
144 #define ADC3XXX_RIGHT_CHN_AGC_1 ADC3XXX_REG(0, 94)
145 #define ADC3XXX_RIGHT_CHN_AGC_2 ADC3XXX_REG(0, 95)
146 #define ADC3XXX_RIGHT_CHN_AGC_3 ADC3XXX_REG(0, 96)
147 #define ADC3XXX_RIGHT_CHN_AGC_4 ADC3XXX_REG(0, 97)
148 #define ADC3XXX_RIGHT_CHN_AGC_5 ADC3XXX_REG(0, 98)
149 #define ADC3XXX_RIGHT_CHN_AGC_6 ADC3XXX_REG(0, 99)
150 #define ADC3XXX_RIGHT_CHN_AGC_7 ADC3XXX_REG(0, 100)
151 #define ADC3XXX_RIGHT_AGC_GAIN ADC3XXX_REG(0, 101)
159 #define ADC3XXX_DITHER_CTRL ADC3XXX_REG(1, 26)
161 #define ADC3XXX_MICBIAS_CTRL ADC3XXX_REG(1, 51)
162 #define ADC3XXX_LEFT_PGA_SEL_1 ADC3XXX_REG(1, 52)
164 #define ADC3XXX_LEFT_PGA_SEL_2 ADC3XXX_REG(1, 54)
165 #define ADC3XXX_RIGHT_PGA_SEL_1 ADC3XXX_REG(1, 55)
166 #define ADC3XXX_RIGHT_PGA_SEL_2 ADC3XXX_REG(1, 57)
167 #define ADC3XXX_LEFT_APGA_CTRL ADC3XXX_REG(1, 59)
168 #define ADC3XXX_RIGHT_APGA_CTRL ADC3XXX_REG(1, 60)
169 #define ADC3XXX_LOW_CURRENT_MODES ADC3XXX_REG(1, 61)
170 #define ADC3XXX_ANALOG_PGA_FLAGS ADC3XXX_REG(1, 62)
176 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 8)
177 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 9)
178 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 10)
179 #define ADC3XXX_LEFT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 11)
180 #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 12)
181 #define ADC3XXX_LEFT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 13)
183 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_MSB ADC3XXX_REG(4, 72)
184 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N0_LSB ADC3XXX_REG(4, 73)
185 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_MSB ADC3XXX_REG(4, 74)
186 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_N1_LSB ADC3XXX_REG(4, 75)
187 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_MSB ADC3XXX_REG(4, 76)
188 #define ADC3XXX_RIGHT_ADC_IIR_COEFF_D1_LSB ADC3XXX_REG(4, 77)