Lines Matching +full:5 +full:ms

46 #define SSM2518_POWER1_NO_BCLK			BIT(5)
61 #define SSM2518_SAI_CTRL1_FMT_MASK		(0x3 << 5)
62 #define SSM2518_SAI_CTRL1_FMT_I2S		(0x0 << 5)
63 #define SSM2518_SAI_CTRL1_FMT_LJ		(0x1 << 5)
64 #define SSM2518_SAI_CTRL1_FMT_RJ_24BIT		(0x2 << 5)
65 #define SSM2518_SAI_CTRL1_FMT_RJ_16BIT		(0x3 << 5)
83 #define SSM2518_SAI_CTRL2_LRCLK_INVERT		BIT(5)
96 #define SSM2518_MUTE_CTRL_ANA_GAIN		BIT(5)
153 	"0 ms", "0.1 ms", "0.19 ms", "0.37 ms", "0.75 ms", "1.5 ms", "3 ms",
154 	"6 ms", "12 ms", "24 ms", "48 ms", "96 ms", "192 ms", "384 ms",
155 	"768 ms", "1536 ms",
159 	"0 ms", "1.5 ms", "3 ms", "6 ms", "12 ms", "24 ms", "48 ms", "96 ms",
160 	"192 ms", "384 ms", "768 ms", "1536 ms", "3072 ms", "6144 ms",
161 	"12288 ms", "24576 ms"
165 	"0 ms", "0.67 ms", "1.33 ms", "2.67 ms", "5.33 ms", "10.66 ms",
166 	"21.32 ms", "42.64 ms", "85.28 ms", "170.56 ms", "341.12 ms",
167 	"682.24 ms", "1364 ms",
195 	SOC_SINGLE("DRC Limiter Switch", SSM2518_REG_DRC_1, 5, 1, 0),