soc/codecs/rt5677.c

153 	{RT5677_PWR_ANLG2		, 0x0000},
303 	case RT5677_PWR_ANLG2: /* Modified by DSP firmware */  in rt5677_volatile_register()
419 	case RT5677_PWR_ANLG2:  in rt5677_readable_register()
777 	regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_set_vad_source()
2575 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_bst1_event()
2580 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_bst1_event()
2599 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_bst2_event()
2604 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_bst2_event()
2667 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_set_micbias1_event()
2674 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_set_micbias1_event()
2773 	SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
2776 	SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
2822 	SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
2861 	SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
2864 	SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
4670 			regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_set_bias_level()
4702 		regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,  in rt5677_set_bias_level()