Lines Matching full:x1
217 #define RT5645_L_MUTE (0x1 << 15)
219 #define RT5645_VOL_L_MUTE (0x1 << 14)
221 #define RT5645_R_MUTE (0x1 << 7)
223 #define RT5645_VOL_R_MUTE (0x1 << 6)
233 #define RT5645_CBJ_JD_HP_EN (0x1 << 9)
234 #define RT5645_CBJ_JD_MIC_EN (0x1 << 8)
235 #define RT5645_CBJ_JD_MIC_SW_EN (0x1 << 7)
236 #define RT5645_CBJ_MIC_SEL_R (0x1 << 6)
237 #define RT5645_CBJ_MIC_SEL_L (0x1 << 5)
238 #define RT5645_CBJ_MIC_SW (0x1 << 4)
239 #define RT5645_CBJ_BST1_EN (0x1 << 2)
242 #define RT5645_CBJ_MN_JD (0x1 << 12)
243 #define RT5645_CAPLESS_EN (0x1 << 11)
244 #define RT5645_CBJ_DET_MODE (0x1 << 7)
247 #define RT5645_CBJ_TIE_G_L (0x1 << 15)
248 #define RT5645_CBJ_TIE_G_R (0x1 << 14)
255 #define RT5645_IN_DF2 (0x1 << 6)
259 #define RT5645_INL_SEL_MASK (0x1 << 15)
262 #define RT5645_INL_SEL_MONOP (0x1 << 15)
265 #define RT5645_INR_SEL_MASK (0x1 << 7)
268 #define RT5645_INR_SEL_MONON (0x1 << 7)
285 #define RT5645_M_DAC_L2_VOL (0x1 << 13)
287 #define RT5645_M_DAC_R2_VOL (0x1 << 12)
323 #define RT5645_STO2_ADC_SRC_MASK (0x1 << 15)
327 #define RT5645_M_ADC_L1 (0x1 << 14)
329 #define RT5645_M_ADC_L2 (0x1 << 13)
331 #define RT5645_ADC_1_SRC_MASK (0x1 << 12)
333 #define RT5645_ADC_1_SRC_ADC (0x1 << 12)
335 #define RT5645_ADC_2_SRC_MASK (0x1 << 11)
337 #define RT5645_DMIC_SRC_MASK (0x1 << 8)
339 #define RT5645_M_ADC_R1 (0x1 << 6)
341 #define RT5645_M_ADC_R2 (0x1 << 5)
343 #define RT5645_DMIC3_SRC_MASK (0x1 << 1)
347 #define RT5645_M_MONO_ADC_L1 (0x1 << 14)
349 #define RT5645_M_MONO_ADC_L2 (0x1 << 13)
351 #define RT5645_MONO_ADC_L1_SRC_MASK (0x1 << 12)
354 #define RT5645_MONO_ADC_L1_SRC_ADCL (0x1 << 12)
355 #define RT5645_MONO_ADC_L2_SRC_MASK (0x1 << 11)
357 #define RT5645_MONO_DMIC_L_SRC_MASK (0x1 << 8)
359 #define RT5645_M_MONO_ADC_R1 (0x1 << 6)
361 #define RT5645_M_MONO_ADC_R2 (0x1 << 5)
363 #define RT5645_MONO_ADC_R1_SRC_MASK (0x1 << 4)
365 #define RT5645_MONO_ADC_R1_SRC_ADCR (0x1 << 4)
367 #define RT5645_MONO_ADC_R2_SRC_MASK (0x1 << 3)
373 #define RT5645_M_ADCMIX_L (0x1 << 15)
375 #define RT5645_M_DAC1_L (0x1 << 14)
380 #define RT5645_DAC1_R_SEL_IF2 (0x1 << 10)
386 #define RT5645_DAC1_L_SEL_IF2 (0x1 << 8)
389 #define RT5645_M_ADCMIX_R (0x1 << 7)
391 #define RT5645_M_DAC1_R (0x1 << 6)
395 #define RT5645_M_DAC_L1 (0x1 << 14)
397 #define RT5645_DAC_L1_STO_L_VOL_MASK (0x1 << 13)
399 #define RT5645_M_DAC_L2 (0x1 << 12)
401 #define RT5645_DAC_L2_STO_L_VOL_MASK (0x1 << 11)
403 #define RT5645_M_ANC_DAC_L (0x1 << 10)
405 #define RT5645_M_DAC_R1_STO_L (0x1 << 9)
407 #define RT5645_DAC_R1_STO_L_VOL_MASK (0x1 << 8)
409 #define RT5645_M_DAC_R1 (0x1 << 6)
411 #define RT5645_DAC_R1_STO_R_VOL_MASK (0x1 << 5)
413 #define RT5645_M_DAC_R2 (0x1 << 4)
415 #define RT5645_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
417 #define RT5645_M_ANC_DAC_R (0x1 << 2)
419 #define RT5645_M_DAC_L1_STO_R (0x1 << 1)
421 #define RT5645_DAC_L1_STO_R_VOL_MASK (0x1)
425 #define RT5645_M_DAC_L1_MONO_L (0x1 << 14)
427 #define RT5645_DAC_L1_MONO_L_VOL_MASK (0x1 << 13)
429 #define RT5645_M_DAC_L2_MONO_L (0x1 << 12)
431 #define RT5645_DAC_L2_MONO_L_VOL_MASK (0x1 << 11)
433 #define RT5645_M_DAC_R2_MONO_L (0x1 << 10)
435 #define RT5645_DAC_R2_MONO_L_VOL_MASK (0x1 << 9)
437 #define RT5645_M_DAC_R1_MONO_R (0x1 << 6)
439 #define RT5645_DAC_R1_MONO_R_VOL_MASK (0x1 << 5)
441 #define RT5645_M_DAC_R2_MONO_R (0x1 << 4)
443 #define RT5645_DAC_R2_MONO_R_VOL_MASK (0x1 << 3)
445 #define RT5645_M_DAC_L2_MONO_R (0x1 << 2)
447 #define RT5645_DAC_L2_MONO_R_VOL_MASK (0x1 << 1)
451 #define RT5645_M_STO_L_DAC_L (0x1 << 15)
453 #define RT5645_STO_L_DAC_L_VOL_MASK (0x1 << 14)
455 #define RT5645_M_DAC_L2_DAC_L (0x1 << 13)
457 #define RT5645_DAC_L2_DAC_L_VOL_MASK (0x1 << 12)
459 #define RT5645_M_STO_R_DAC_R (0x1 << 11)
461 #define RT5645_STO_R_DAC_R_VOL_MASK (0x1 << 10)
463 #define RT5645_M_DAC_R2_DAC_R (0x1 << 9)
465 #define RT5645_DAC_R2_DAC_R_VOL_MASK (0x1 << 8)
467 #define RT5645_M_DAC_R2_DAC_L (0x1 << 7)
469 #define RT5645_DAC_R2_DAC_L_VOL_MASK (0x1 << 6)
471 #define RT5645_M_DAC_L2_DAC_R (0x1 << 5)
473 #define RT5645_DAC_L2_DAC_R_VOL_MASK (0x1 << 4)
483 #define RT5645_IF1_ADC2_IN_SEL (0x1 << 15)
499 #define RT5645_PDM1_L_MASK (0x1 << 15)
501 #define RT5645_M_PDM1_L (0x1 << 14)
503 #define RT5645_PDM1_R_MASK (0x1 << 13)
505 #define RT5645_M_PDM1_R (0x1 << 12)
507 #define RT5645_PDM2_L_MASK (0x1 << 11)
509 #define RT5645_M_PDM2_L (0x1 << 10)
511 #define RT5645_PDM2_R_MASK (0x1 << 9)
513 #define RT5645_M_PDM2_R (0x1 << 8)
515 #define RT5645_PDM2_BUSY (0x1 << 7)
516 #define RT5645_PDM1_BUSY (0x1 << 6)
517 #define RT5645_PDM_PATTERN (0x1 << 5)
518 #define RT5645_PDM_GAIN (0x1 << 4)
538 #define RT5645_M_MM_L_RM_L (0x1 << 6)
540 #define RT5645_M_IN_L_RM_L (0x1 << 5)
542 #define RT5645_M_HP_L_RM_L (0x1 << 4)
544 #define RT5645_M_BST3_RM_L (0x1 << 3)
546 #define RT5645_M_BST2_RM_L (0x1 << 2)
548 #define RT5645_M_BST1_RM_L (0x1 << 1)
550 #define RT5645_M_OM_L_RM_L (0x1)
570 #define RT5645_M_MM_R_RM_R (0x1 << 6)
572 #define RT5645_M_IN_R_RM_R (0x1 << 5)
574 #define RT5645_M_HP_R_RM_R (0x1 << 4)
576 #define RT5645_M_BST3_RM_R (0x1 << 3)
578 #define RT5645_M_BST2_RM_R (0x1 << 2)
580 #define RT5645_M_BST1_RM_R (0x1 << 1)
582 #define RT5645_M_OM_R_RM_R (0x1)
586 #define RT5645_M_BST1_HV (0x1 << 4)
588 #define RT5645_M_BST2_HV (0x1 << 4)
590 #define RT5645_M_BST3_HV (0x1 << 3)
592 #define RT5645_M_IN_HV (0x1 << 2)
594 #define RT5645_M_DAC2_HV (0x1 << 1)
596 #define RT5645_M_DAC1_HV (0x1 << 0)
600 #define RT5645_M_DAC1_HM (0x1 << 14)
602 #define RT5645_M_HPVOL_HM (0x1 << 13)
604 #define RT5645_IRQ_PSV_MODE (0x1 << 12)
617 #define RT5645_M_BST1_L_SM_L (0x1 << 5)
619 #define RT5645_M_BST3_L_SM_L (0x1 << 4)
621 #define RT5645_M_IN_L_SM_L (0x1 << 3)
623 #define RT5645_M_DAC_L2_SM_L (0x1 << 2)
625 #define RT5645_M_DAC_L1_SM_L (0x1 << 1)
639 #define RT5645_M_BST2_R_SM_R (0x1 << 5)
641 #define RT5645_M_BST3_R_SM_R (0x1 << 4)
643 #define RT5645_M_IN_R_SM_R (0x1 << 3)
645 #define RT5645_M_DAC_R2_SM_R (0x1 << 2)
647 #define RT5645_M_DAC_R1_SM_R (0x1 << 1)
651 #define RT5645_M_DAC_L1_SPM_L (0x1 << 15)
653 #define RT5645_M_DAC_R1_SPM_L (0x1 << 14)
655 #define RT5645_M_SV_L_SPM_L (0x1 << 13)
657 #define RT5645_M_SV_R_SPM_L (0x1 << 12)
659 #define RT5645_M_BST3_SPM_L (0x1 << 11)
661 #define RT5645_M_DAC_R1_SPM_R (0x1 << 2)
663 #define RT5645_M_BST3_SPM_R (0x1 << 1)
665 #define RT5645_M_SV_R_SPM_R (0x1 << 0)
673 #define RT5645_G_MONOMIX_MASK (0x1 << 10)
675 #define RT5645_M_OV_L_MM (0x1 << 9)
677 #define RT5645_M_DAC_L2_MA (0x1 << 8)
679 #define RT5645_M_BST2_MM (0x1 << 4)
681 #define RT5645_M_DAC_R1_MM (0x1 << 3)
683 #define RT5645_M_DAC_R2_MM (0x1 << 2)
685 #define RT5645_M_DAC_L2_MM (0x1 << 1)
687 #define RT5645_M_BST3_MM (0x1 << 0)
711 #define RT5645_M_BST3_OM_L (0x1 << 4)
713 #define RT5645_M_BST1_OM_L (0x1 << 3)
715 #define RT5645_M_IN_L_OM_L (0x1 << 2)
717 #define RT5645_M_DAC_L2_OM_L (0x1 << 1)
719 #define RT5645_M_DAC_L1_OM_L (0x1)
743 #define RT5645_M_BST3_OM_R (0x1 << 4)
745 #define RT5645_M_BST2_OM_R (0x1 << 3)
747 #define RT5645_M_IN_R_OM_R (0x1 << 2)
749 #define RT5645_M_DAC_R2_OM_R (0x1 << 1)
751 #define RT5645_M_DAC_R1_OM_R (0x1)
755 #define RT5645_M_DAC_L1_LM (0x1 << 15)
757 #define RT5645_M_DAC_R1_LM (0x1 << 14)
759 #define RT5645_M_OV_L_LM (0x1 << 13)
761 #define RT5645_M_OV_R_LM (0x1 << 12)
763 #define RT5645_G_LOUTMIX_MASK (0x1 << 11)
767 #define RT5645_PWR_I2S1 (0x1 << 15)
769 #define RT5645_PWR_I2S2 (0x1 << 14)
771 #define RT5645_PWR_I2S3 (0x1 << 13)
773 #define RT5645_PWR_DAC_L1 (0x1 << 12)
775 #define RT5645_PWR_DAC_R1 (0x1 << 11)
777 #define RT5645_PWR_CLS_D_R (0x1 << 9)
779 #define RT5645_PWR_CLS_D_L (0x1 << 8)
781 #define RT5645_PWR_DAC_L2 (0x1 << 7)
783 #define RT5645_PWR_DAC_R2 (0x1 << 6)
785 #define RT5645_PWR_ADC_L (0x1 << 2)
787 #define RT5645_PWR_ADC_R (0x1 << 1)
789 #define RT5645_PWR_CLS_D (0x1)
793 #define RT5645_PWR_ADC_S1F (0x1 << 15)
795 #define RT5645_PWR_ADC_MF_L (0x1 << 14)
797 #define RT5645_PWR_ADC_MF_R (0x1 << 13)
799 #define RT5645_PWR_I2S_DSP (0x1 << 12)
801 #define RT5645_PWR_DAC_S1F (0x1 << 11)
803 #define RT5645_PWR_DAC_MF_L (0x1 << 10)
805 #define RT5645_PWR_DAC_MF_R (0x1 << 9)
807 #define RT5645_PWR_PDM1 (0x1 << 7)
809 #define RT5645_PWR_PDM2 (0x1 << 6)
811 #define RT5645_PWR_IPTV (0x1 << 1)
813 #define RT5645_PWR_PAD (0x1)
817 #define RT5645_PWR_VREF1 (0x1 << 15)
819 #define RT5645_PWR_FV1 (0x1 << 14)
821 #define RT5645_PWR_MB (0x1 << 13)
823 #define RT5645_PWR_LM (0x1 << 12)
825 #define RT5645_PWR_BG (0x1 << 11)
827 #define RT5645_PWR_MA (0x1 << 10)
829 #define RT5645_PWR_HP_L (0x1 << 7)
831 #define RT5645_PWR_HP_R (0x1 << 6)
833 #define RT5645_PWR_HA (0x1 << 5)
835 #define RT5645_PWR_VREF2 (0x1 << 4)
837 #define RT5645_PWR_FV2 (0x1 << 3)
843 #define RT5645_PWR_BST1 (0x1 << 15)
845 #define RT5645_PWR_BST2 (0x1 << 14)
847 #define RT5645_PWR_BST3 (0x1 << 13)
849 #define RT5645_PWR_BST4 (0x1 << 12)
851 #define RT5645_PWR_MB1 (0x1 << 11)
853 #define RT5645_PWR_MB2 (0x1 << 10)
855 #define RT5645_PWR_PLL (0x1 << 9)
857 #define RT5645_PWR_BST2_P (0x1 << 5)
859 #define RT5645_PWR_BST3_P (0x1 << 4)
861 #define RT5645_PWR_BST4_P (0x1 << 3)
863 #define RT5645_PWR_JD1 (0x1 << 2)
865 #define RT5645_PWR_JD (0x1 << 1)
869 #define RT5645_PWR_OM_L (0x1 << 15)
871 #define RT5645_PWR_OM_R (0x1 << 14)
873 #define RT5645_PWR_SM_L (0x1 << 13)
875 #define RT5645_PWR_SM_R (0x1 << 12)
877 #define RT5645_PWR_RM_L (0x1 << 11)
879 #define RT5645_PWR_RM_R (0x1 << 10)
881 #define RT5645_PWR_MM (0x1 << 8)
883 #define RT5645_PWR_HM_L (0x1 << 7)
885 #define RT5645_PWR_HM_R (0x1 << 6)
887 #define RT5645_PWR_LDO2 (0x1 << 1)
891 #define RT5645_PWR_SV_L (0x1 << 15)
893 #define RT5645_PWR_SV_R (0x1 << 14)
895 #define RT5645_PWR_HV_L (0x1 << 11)
897 #define RT5645_PWR_HV_R (0x1 << 10)
899 #define RT5645_PWR_IN_L (0x1 << 9)
901 #define RT5645_PWR_IN_R (0x1 << 8)
903 #define RT5645_PWR_MIC_DET (0x1 << 5)
907 #define RT5645_I2S_MS_MASK (0x1 << 15)
910 #define RT5645_I2S_MS_S (0x1 << 15)
914 #define RT5645_I2S_O_CP_U_LAW (0x1 << 10)
919 #define RT5645_I2S_I_CP_U_LAW (0x1 << 8)
921 #define RT5645_I2S_BP_MASK (0x1 << 7)
924 #define RT5645_I2S_BP_INV (0x1 << 7)
928 #define RT5645_I2S_DL_20 (0x1 << 2)
934 #define RT5645_I2S_DF_LEFT (0x1)
939 #define RT5645_I2S2_SDI_MASK (0x1 << 6)
942 #define RT5645_I2S2_SDI_I2S2 (0x1 << 6)
948 #define RT5645_I2S_PD1_2 (0x1 << 12)
955 #define RT5645_I2S_BCLK_MS2_MASK (0x1 << 11)
958 #define RT5645_I2S_BCLK_MS2_64 (0x1 << 11)
962 #define RT5645_I2S_PD2_2 (0x1 << 8)
969 #define RT5645_I2S_BCLK_MS3_MASK (0x1 << 7)
972 #define RT5645_I2S_BCLK_MS3_64 (0x1 << 7)
976 #define RT5645_I2S_PD3_2 (0x1 << 4)
986 #define RT5645_DAC_OSR_64 (0x1 << 2)
992 #define RT5645_ADC_OSR_64 (0x1)
1000 #define RT5645_DAC_L_OSR_64 (0x1 << 14)
1006 #define RT5645_ADC_R_OSR_64 (0x1 << 12)
1009 #define RT5645_DAHPF_EN (0x1 << 11)
1011 #define RT5645_ADHPF_EN (0x1 << 10)
1015 #define RT5645_DMIC_1_EN_MASK (0x1 << 15)
1018 #define RT5645_DMIC_1_EN (0x1 << 15)
1019 #define RT5645_DMIC_2_EN_MASK (0x1 << 14)
1022 #define RT5645_DMIC_2_EN (0x1 << 14)
1023 #define RT5645_DMIC_1L_LH_MASK (0x1 << 13)
1026 #define RT5645_DMIC_1L_LH_RISING (0x1 << 13)
1027 #define RT5645_DMIC_1R_LH_MASK (0x1 << 12)
1030 #define RT5645_DMIC_1R_LH_RISING (0x1 << 12)
1034 #define RT5645_DMIC_2_DP_GPIO10 (0x1 << 10)
1037 #define RT5645_DMIC_2L_LH_MASK (0x1 << 9)
1040 #define RT5645_DMIC_2L_LH_RISING (0x1 << 9)
1041 #define RT5645_DMIC_2R_LH_MASK (0x1 << 8)
1044 #define RT5645_DMIC_2R_LH_RISING (0x1 << 8)
1047 #define RT5645_DMIC_3_EN_MASK (0x1 << 4)
1050 #define RT5645_DMIC_3_EN (0x1 << 4)
1054 #define RT5645_DMIC_1_DP_IN2N (0x1 << 0)
1065 #define RT5645_SCLK_SRC_PLL1 (0x1 << 14)
1070 #define RT5645_PLL1_SRC_BCLK1 (0x1 << 11)
1074 #define RT5645_PLL1_PD_MASK (0x1 << 3)
1077 #define RT5645_PLL1_PD_2 (0x1 << 3)
1093 #define RT5645_PLL_M_BP (0x1 << 11)
1097 #define RT5645_STO_T_MASK (0x1 << 15)
1100 #define RT5645_STO_T_LRCK1 (0x1 << 15)
1101 #define RT5645_M1_T_MASK (0x1 << 14)
1104 #define RT5645_M1_T_I2S2_D3 (0x1 << 14)
1105 #define RT5645_I2S2_F_MASK (0x1 << 12)
1108 #define RT5645_I2S2_F_I2S1_TCLK (0x1 << 12)
1109 #define RT5645_DMIC_1_M_MASK (0x1 << 9)
1112 #define RT5645_DMIC_1_M_ASYN (0x1 << 9)
1113 #define RT5645_DMIC_2_M_MASK (0x1 << 8)
1116 #define RT5645_DMIC_2_M_ASYN (0x1 << 8)
1120 #define RT5645_CLK_SEL_I2S1_ASRC (0x1)
1147 #define RT5645_HP_OVCD_MASK (0x1 << 10)
1150 #define RT5645_HP_OVCD_EN (0x1 << 10)
1154 #define RT5645_HP_OC_TH_105 (0x1 << 8)
1159 #define RT5645_CLSD_OC_MASK (0x1 << 9)
1162 #define RT5645_CLSD_OC_PD (0x1 << 9)
1163 #define RT5645_AUTO_PD_MASK (0x1 << 8)
1166 #define RT5645_AUTO_PD_EN (0x1 << 8)
1173 #define RT5645_CLSD_OM_MASK (0x1 << 11)
1176 #define RT5645_CLSD_OM_STO (0x1 << 11)
1177 #define RT5645_CLSD_SCH_MASK (0x1 << 10)
1180 #define RT5645_CLSD_SCH_S (0x1 << 10)
1183 #define RT5645_SMT_TRIG_MASK (0x1 << 15)
1186 #define RT5645_SMT_TRIG_EN (0x1 << 15)
1187 #define RT5645_HP_L_SMT_MASK (0x1 << 9)
1190 #define RT5645_HP_L_SMT_EN (0x1 << 9)
1191 #define RT5645_HP_R_SMT_MASK (0x1 << 8)
1194 #define RT5645_HP_R_SMT_EN (0x1 << 8)
1195 #define RT5645_HP_CD_PD_MASK (0x1 << 7)
1198 #define RT5645_HP_CD_PD_EN (0x1 << 7)
1199 #define RT5645_RSTN_MASK (0x1 << 6)
1202 #define RT5645_RSTN_EN (0x1 << 6)
1203 #define RT5645_RSTP_MASK (0x1 << 5)
1206 #define RT5645_RSTP_EN (0x1 << 5)
1207 #define RT5645_HP_CO_MASK (0x1 << 4)
1210 #define RT5645_HP_CO_EN (0x1 << 4)
1211 #define RT5645_HP_CP_MASK (0x1 << 3)
1214 #define RT5645_HP_CP_PU (0x1 << 3)
1215 #define RT5645_HP_SG_MASK (0x1 << 2)
1218 #define RT5645_HP_SG_EN (0x1 << 2)
1219 #define RT5645_HP_DP_MASK (0x1 << 1)
1222 #define RT5645_HP_DP_PU (0x1 << 1)
1223 #define RT5645_HP_CB_MASK (0x1)
1226 #define RT5645_HP_CB_PU (0x1)
1229 #define RT5645_DEPOP_MASK (0x1 << 13)
1232 #define RT5645_DEPOP_MAN (0x1 << 13)
1233 #define RT5645_RAMP_MASK (0x1 << 12)
1236 #define RT5645_RAMP_EN (0x1 << 12)
1237 #define RT5645_BPS_MASK (0x1 << 11)
1240 #define RT5645_BPS_EN (0x1 << 11)
1241 #define RT5645_FAST_UPDN_MASK (0x1 << 10)
1244 #define RT5645_FAST_UPDN_EN (0x1 << 10)
1248 #define RT5645_MRES_25MO (0x1 << 8)
1251 #define RT5645_VLO_MASK (0x1 << 7)
1254 #define RT5645_VLO_32V (0x1 << 7)
1255 #define RT5645_DIG_DP_MASK (0x1 << 6)
1258 #define RT5645_DIG_DP_EN (0x1 << 6)
1281 #define RT5645_PVDD_DET_MASK (0x1 << 15)
1284 #define RT5645_PVDD_DET_EN (0x1 << 15)
1285 #define RT5645_SPK_AG_MASK (0x1 << 14)
1288 #define RT5645_SPK_AG_EN (0x1 << 14)
1291 #define RT5645_MIC1_BS_MASK (0x1 << 15)
1294 #define RT5645_MIC1_BS_75AV (0x1 << 15)
1295 #define RT5645_MIC2_BS_MASK (0x1 << 14)
1298 #define RT5645_MIC2_BS_75AV (0x1 << 14)
1299 #define RT5645_MIC1_CLK_MASK (0x1 << 13)
1302 #define RT5645_MIC1_CLK_EN (0x1 << 13)
1303 #define RT5645_MIC2_CLK_MASK (0x1 << 12)
1306 #define RT5645_MIC2_CLK_EN (0x1 << 12)
1307 #define RT5645_MIC1_OVCD_MASK (0x1 << 11)
1310 #define RT5645_MIC1_OVCD_EN (0x1 << 11)
1314 #define RT5645_MIC1_OVTH_1500UA (0x1 << 9)
1316 #define RT5645_MIC2_OVCD_MASK (0x1 << 8)
1319 #define RT5645_MIC2_OVCD_EN (0x1 << 8)
1323 #define RT5645_MIC2_OVTH_1500UA (0x1 << 6)
1325 #define RT5645_PWR_MB_MASK (0x1 << 5)
1328 #define RT5645_PWR_MB_PU (0x1 << 5)
1329 #define RT5645_PWR_CLK25M_MASK (0x1 << 4)
1332 #define RT5645_PWR_CLK25M_PU (0x1 << 4)
1334 #define RT5645_IRQ_CLK_INT (0x1 << 3)
1337 #define RT5645_JD1_MODE_1 (0x1 << 0)
1345 #define RT5645_EQ_SRC_MASK (0x1 << 15)
1348 #define RT5645_EQ_SRC_ADC (0x1 << 15)
1349 #define RT5645_EQ_UPD (0x1 << 14)
1351 #define RT5645_EQ_CD_MASK (0x1 << 13)
1354 #define RT5645_EQ_CD_EN (0x1 << 13)
1358 #define RT5645_EQ_DITH_LSB (0x1 << 8)
1363 #define RT5645_EQ_HPF1_M_MASK (0x1 << 8)
1366 #define RT5645_EQ_HPF1_M_1ST (0x1 << 8)
1367 #define RT5645_EQ_LPF1_M_MASK (0x1 << 7)
1370 #define RT5645_EQ_LPF1_M_1ST (0x1 << 7)
1371 #define RT5645_EQ_HPF2_MASK (0x1 << 6)
1374 #define RT5645_EQ_HPF2_EN (0x1 << 6)
1375 #define RT5645_EQ_HPF1_MASK (0x1 << 5)
1378 #define RT5645_EQ_HPF1_EN (0x1 << 5)
1379 #define RT5645_EQ_BPF4_MASK (0x1 << 4)
1382 #define RT5645_EQ_BPF4_EN (0x1 << 4)
1383 #define RT5645_EQ_BPF3_MASK (0x1 << 3)
1386 #define RT5645_EQ_BPF3_EN (0x1 << 3)
1387 #define RT5645_EQ_BPF2_MASK (0x1 << 2)
1390 #define RT5645_EQ_BPF2_EN (0x1 << 2)
1391 #define RT5645_EQ_BPF1_MASK (0x1 << 1)
1394 #define RT5645_EQ_BPF1_EN (0x1 << 1)
1395 #define RT5645_EQ_LPF_MASK (0x1)
1398 #define RT5645_EQ_LPF_EN (0x1)
1402 #define RT5645_MT_MASK (0x1 << 15)
1405 #define RT5645_MT_EN (0x1 << 15)
1408 #define RT5645_DRC_AGC_P_MASK (0x1 << 15)
1411 #define RT5645_DRC_AGC_P_ADC (0x1 << 15)
1412 #define RT5645_DRC_AGC_MASK (0x1 << 14)
1415 #define RT5645_DRC_AGC_EN (0x1 << 14)
1416 #define RT5645_DRC_AGC_UPD (0x1 << 13)
1422 #define RT5645_DRC_AGC_R_48K (0x1 << 5)
1434 #define RT5645_DRC_AGC_CP_MASK (0x1 << 7)
1437 #define RT5645_DRC_AGC_CP_EN (0x1 << 7)
1441 #define RT5645_DRC_AGC_CPR_1_2 (0x1 << 5)
1452 #define RT5645_DRC_AGC_NG_MASK (0x1 << 6)
1455 #define RT5645_DRC_AGC_NG_EN (0x1 << 6)
1456 #define RT5645_DRC_AGC_NGH_MASK (0x1 << 5)
1459 #define RT5645_DRC_AGC_NGH_EN (0x1 << 5)
1464 #define RT5645_ANC_M_MASK (0x1 << 15)
1467 #define RT5645_ANC_M_REV (0x1 << 15)
1468 #define RT5645_ANC_MASK (0x1 << 14)
1471 #define RT5645_ANC_EN (0x1 << 14)
1475 #define RT5645_ANC_MD_67MS (0x1 << 12)
1478 #define RT5645_ANC_SN_MASK (0x1 << 11)
1481 #define RT5645_ANC_SN_EN (0x1 << 11)
1482 #define RT5645_ANC_CLK_MASK (0x1 << 10)
1485 #define RT5645_ANC_CLK_REG (0x1 << 10)
1489 #define RT5645_ANC_ZCD_T1 (0x1 << 8)
1492 #define RT5645_ANC_CS_MASK (0x1 << 7)
1495 #define RT5645_ANC_CS_EN (0x1 << 7)
1496 #define RT5645_ANC_SW_MASK (0x1 << 6)
1499 #define RT5645_ANC_SW_AUTO (0x1 << 6)
1514 #define RT5645_ANC_CD_MASK (0x1 << 6)
1517 #define RT5645_ANC_CD_IND (0x1 << 6)
1525 #define RT5645_JD_GPIO1 (0x1 << 13)
1531 #define RT5645_JD_HP_MASK (0x1 << 11)
1534 #define RT5645_JD_HP_EN (0x1 << 11)
1535 #define RT5645_JD_HP_TRG_MASK (0x1 << 10)
1538 #define RT5645_JD_HP_TRG_HI (0x1 << 10)
1539 #define RT5645_JD_SPL_MASK (0x1 << 9)
1542 #define RT5645_JD_SPL_EN (0x1 << 9)
1543 #define RT5645_JD_SPL_TRG_MASK (0x1 << 8)
1546 #define RT5645_JD_SPL_TRG_HI (0x1 << 8)
1547 #define RT5645_JD_SPR_MASK (0x1 << 7)
1550 #define RT5645_JD_SPR_EN (0x1 << 7)
1551 #define RT5645_JD_SPR_TRG_MASK (0x1 << 6)
1554 #define RT5645_JD_SPR_TRG_HI (0x1 << 6)
1555 #define RT5645_JD_MO_MASK (0x1 << 5)
1558 #define RT5645_JD_MO_EN (0x1 << 5)
1559 #define RT5645_JD_MO_TRG_MASK (0x1 << 4)
1562 #define RT5645_JD_MO_TRG_HI (0x1 << 4)
1563 #define RT5645_JD_LO_MASK (0x1 << 3)
1566 #define RT5645_JD_LO_EN (0x1 << 3)
1567 #define RT5645_JD_LO_TRG_MASK (0x1 << 2)
1570 #define RT5645_JD_LO_TRG_HI (0x1 << 2)
1571 #define RT5645_JD1_IN4P_MASK (0x1 << 1)
1574 #define RT5645_JD1_IN4P_EN (0x1 << 1)
1575 #define RT5645_JD2_IN4N_MASK (0x1)
1578 #define RT5645_JD2_IN4N_EN (0x1)
1584 #define RT5645_ANC_DET_MB1 (0x1 << 4)
1587 #define RT5645_AD_TRG_MASK (0x1 << 3)
1590 #define RT5645_AD_TRG_HI (0x1 << 3)
1594 #define RT5645_ANCM_DET_MB1 (0x1 << 4)
1597 #define RT5645_AMD_TRG_MASK (0x1 << 3)
1600 #define RT5645_AMD_TRG_HI (0x1 << 3)
1603 #define RT5645_IRQ_JD_MASK (0x1 << 15)
1606 #define RT5645_IRQ_JD_NOR (0x1 << 15)
1607 #define RT5645_IRQ_OT_MASK (0x1 << 14)
1610 #define RT5645_IRQ_OT_NOR (0x1 << 14)
1611 #define RT5645_JD_STKY_MASK (0x1 << 13)
1614 #define RT5645_JD_STKY_EN (0x1 << 13)
1615 #define RT5645_OT_STKY_MASK (0x1 << 12)
1618 #define RT5645_OT_STKY_EN (0x1 << 12)
1619 #define RT5645_JD_P_MASK (0x1 << 11)
1622 #define RT5645_JD_P_INV (0x1 << 11)
1623 #define RT5645_OT_P_MASK (0x1 << 10)
1626 #define RT5645_OT_P_INV (0x1 << 10)
1627 #define RT5645_IRQ_JD_1_1_EN (0x1 << 9)
1628 #define RT5645_JD_1_1_MASK (0x1 << 7)
1631 #define RT5645_JD_1_1_INV (0x1 << 7)
1634 #define RT5645_IRQ_MB1_OC_MASK (0x1 << 15)
1637 #define RT5645_IRQ_MB1_OC_NOR (0x1 << 15)
1638 #define RT5645_IRQ_MB2_OC_MASK (0x1 << 14)
1641 #define RT5645_IRQ_MB2_OC_NOR (0x1 << 14)
1642 #define RT5645_MB1_OC_STKY_MASK (0x1 << 13)
1645 #define RT5645_MB1_OC_STKY_EN (0x1 << 13)
1646 #define RT5645_MB2_OC_STKY_MASK (0x1 << 12)
1649 #define RT5645_MB2_OC_STKY_EN (0x1 << 12)
1650 #define RT5645_MB1_OC_P_MASK (0x1 << 7)
1653 #define RT5645_MB1_OC_P_INV (0x1 << 7)
1654 #define RT5645_MB2_OC_P_MASK (0x1 << 6)
1657 #define RT5645_MB2_OC_P_INV (0x1 << 6)
1658 #define RT5645_MB1_OC_CLR (0x1 << 3)
1660 #define RT5645_MB2_OC_CLR (0x1 << 2)
1664 #define RT5645_GP1_PIN_MASK (0x1 << 15)
1667 #define RT5645_GP1_PIN_IRQ (0x1 << 15)
1668 #define RT5645_GP2_PIN_MASK (0x1 << 14)
1671 #define RT5645_GP2_PIN_DMIC1_SCL (0x1 << 14)
1675 #define RT5645_GP3_PIN_DMIC1_SDA (0x1 << 12)
1677 #define RT5645_GP4_PIN_MASK (0x1 << 11)
1680 #define RT5645_GP4_PIN_DMIC2_SDA (0x1 << 11)
1681 #define RT5645_DP_SIG_MASK (0x1 << 10)
1684 #define RT5645_DP_SIG_AP (0x1 << 10)
1685 #define RT5645_GPIO_M_MASK (0x1 << 9)
1688 #define RT5645_GPIO_M_PH (0x1 << 9)
1689 #define RT5645_I2S2_SEL (0x1 << 8)
1691 #define RT5645_GP5_PIN_MASK (0x1 << 7)
1694 #define RT5645_GP5_PIN_DMIC1_SDA (0x1 << 7)
1695 #define RT5645_GP6_PIN_MASK (0x1 << 6)
1698 #define RT5645_GP6_PIN_DMIC2_SDA (0x1 << 6)
1699 #define RT5645_I2S2_DAC_PIN_MASK (0x1 << 4)
1702 #define RT5645_I2S2_DAC_PIN_GPIO (0x1 << 4)
1703 #define RT5645_GP8_PIN_MASK (0x1 << 3)
1706 #define RT5645_GP8_PIN_DMIC2_SDA (0x1 << 3)
1707 #define RT5645_GP12_PIN_MASK (0x1 << 2)
1710 #define RT5645_GP12_PIN_DMIC2_SDA (0x1 << 2)
1711 #define RT5645_GP11_PIN_MASK (0x1 << 1)
1714 #define RT5645_GP11_PIN_DMIC1_SDA (0x1 << 1)
1715 #define RT5645_GP10_PIN_MASK (0x1)
1718 #define RT5645_GP10_PIN_DMIC2_SDA (0x1)
1721 #define RT5645_GP4_PF_MASK (0x1 << 11)
1724 #define RT5645_GP4_PF_OUT (0x1 << 11)
1725 #define RT5645_GP4_OUT_MASK (0x1 << 10)
1728 #define RT5645_GP4_OUT_HI (0x1 << 10)
1729 #define RT5645_GP4_P_MASK (0x1 << 9)
1732 #define RT5645_GP4_P_INV (0x1 << 9)
1733 #define RT5645_GP3_PF_MASK (0x1 << 8)
1736 #define RT5645_GP3_PF_OUT (0x1 << 8)
1737 #define RT5645_GP3_OUT_MASK (0x1 << 7)
1740 #define RT5645_GP3_OUT_HI (0x1 << 7)
1741 #define RT5645_GP3_P_MASK (0x1 << 6)
1744 #define RT5645_GP3_P_INV (0x1 << 6)
1745 #define RT5645_GP2_PF_MASK (0x1 << 5)
1748 #define RT5645_GP2_PF_OUT (0x1 << 5)
1749 #define RT5645_GP2_OUT_MASK (0x1 << 4)
1752 #define RT5645_GP2_OUT_HI (0x1 << 4)
1753 #define RT5645_GP2_P_MASK (0x1 << 3)
1756 #define RT5645_GP2_P_INV (0x1 << 3)
1757 #define RT5645_GP1_PF_MASK (0x1 << 2)
1760 #define RT5645_GP1_PF_OUT (0x1 << 2)
1761 #define RT5645_GP1_OUT_MASK (0x1 << 1)
1764 #define RT5645_GP1_OUT_HI (0x1 << 1)
1765 #define RT5645_GP1_P_MASK (0x1)
1768 #define RT5645_GP1_P_INV (0x1)
1773 #define RT5645_SEQ1_ST_MASK (0x1 << 11) /*RO*/
1776 #define RT5645_SEQ1_ST_FIN (0x1 << 11)
1777 #define RT5645_SEQ2_ST_MASK (0x1 << 10) /*RO*/
1780 #define RT5645_SEQ2_ST_FIN (0x1 << 10)
1781 #define RT5645_REG_LV_MASK (0x1 << 9)
1784 #define RT5645_REG_LV_PR (0x1 << 9)
1785 #define RT5645_SEQ_2_PT_MASK (0x1 << 8)
1797 #define RT5645_PROG_MASK (0x1 << 7)
1800 #define RT5645_PROG_EN (0x1 << 7)
1801 #define RT5645_SEQ1_PT_RUN (0x1 << 6)
1803 #define RT5645_SEQ2_PT_RUN (0x1 << 5)
1823 #define RT5645_SCB_SWAP_MASK (0x1 << 15)
1826 #define RT5645_SCB_SWAP_EN (0x1 << 15)
1827 #define RT5645_SCB_MASK (0x1 << 14)
1830 #define RT5645_SCB_EN (0x1 << 14)
1833 #define RT5645_BB_MASK (0x1 << 15)
1836 #define RT5645_BB_EN (0x1 << 15)
1840 #define RT5645_BB_CT_B (0x1 << 12)
1843 #define RT5645_M_BB_L_MASK (0x1 << 9)
1845 #define RT5645_M_BB_R_MASK (0x1 << 8)
1847 #define RT5645_M_BB_HPF_L_MASK (0x1 << 7)
1849 #define RT5645_M_BB_HPF_R_MASK (0x1 << 6)
1856 #define RT5645_M_MP3_L_MASK (0x1 << 15)
1858 #define RT5645_M_MP3_R_MASK (0x1 << 14)
1860 #define RT5645_M_MP3_MASK (0x1 << 13)
1863 #define RT5645_M_MP3_EN (0x1 << 13)
1866 #define RT5645_MP3_HLP_MASK (0x1 << 7)
1869 #define RT5645_MP3_HLP_EN (0x1 << 7)
1870 #define RT5645_M_MP3_ORG_L_MASK (0x1 << 6)
1872 #define RT5645_M_MP3_ORG_R_MASK (0x1 << 5)
1876 #define RT5645_MP3_WT_MASK (0x1 << 13)
1879 #define RT5645_MP3_WT_1_2 (0x1 << 13)
1886 #define RT5645_3D_CF_MASK (0x1 << 15)
1889 #define RT5645_3D_CF_EN (0x1 << 15)
1890 #define RT5645_3D_HP_MASK (0x1 << 14)
1893 #define RT5645_3D_HP_EN (0x1 << 14)
1894 #define RT5645_3D_BT_MASK (0x1 << 13)
1897 #define RT5645_3D_BT_EN (0x1 << 13)
1900 #define RT5645_3D_HP_M_MASK (0x1 << 10)
1903 #define RT5645_3D_HP_M_FRO (0x1 << 10)
1904 #define RT5645_M_3D_HRTF_MASK (0x1 << 9)
1906 #define RT5645_M_3D_D2H_MASK (0x1 << 8)
1908 #define RT5645_M_3D_D2R_MASK (0x1 << 7)
1910 #define RT5645_M_3D_REVB_MASK (0x1 << 6)
1914 #define RT5645_2ND_HPF_MASK (0x1 << 15)
1917 #define RT5645_2ND_HPF_EN (0x1 << 15)
1920 #define RT5645_1ST_HPF_MASK (0x1 << 11)
1923 #define RT5645_1ST_HPF_EN (0x1 << 11)
1931 #define RT5645_ZD_F_ZC_IM (0x1 << 4)
1936 #define RT5645_SI_DAC_MASK (0x1 << 11)
1939 #define RT5645_SI_DAC_TEST (0x1 << 11)
1940 #define RT5645_DC_CAL_M_MASK (0x1 << 10)
1943 #define RT5645_DC_CAL_M_NOR (0x1 << 10)
1944 #define RT5645_DC_CAL_MASK (0x1 << 9)
1947 #define RT5645_DC_CAL_EN (0x1 << 9)
1950 #define RT5645_HPD_PS_MASK (0x1 << 5)
1953 #define RT5645_HPD_PS_EN (0x1 << 5)
1954 #define RT5645_CAL_M_MASK (0x1 << 4)
1957 #define RT5645_CAL_M_CAL (0x1 << 4)
1958 #define RT5645_CAL_MASK (0x1 << 3)
1961 #define RT5645_CAL_EN (0x1 << 3)
1962 #define RT5645_CAL_TEST_MASK (0x1 << 2)
1965 #define RT5645_CAL_TEST_EN (0x1 << 2)
1969 #define RT5645_CAL_P_CAL (0x1)
1973 #define RT5645_SV_MASK (0x1 << 15)
1976 #define RT5645_SV_EN (0x1 << 15)
1977 #define RT5645_SPO_SV_MASK (0x1 << 14)
1980 #define RT5645_SPO_SV_EN (0x1 << 14)
1981 #define RT5645_OUT_SV_MASK (0x1 << 13)
1984 #define RT5645_OUT_SV_EN (0x1 << 13)
1985 #define RT5645_HP_SV_MASK (0x1 << 12)
1988 #define RT5645_HP_SV_EN (0x1 << 12)
1989 #define RT5645_ZCD_DIG_MASK (0x1 << 11)
1992 #define RT5645_ZCD_DIG_EN (0x1 << 11)
1993 #define RT5645_ZCD_MASK (0x1 << 10)
1996 #define RT5645_ZCD_PU (0x1 << 10)
1999 #define RT5645_M_ZCD_RM_L (0x1 << 9)
2000 #define RT5645_M_ZCD_RM_R (0x1 << 8)
2001 #define RT5645_M_ZCD_SM_L (0x1 << 7)
2002 #define RT5645_M_ZCD_SM_R (0x1 << 6)
2003 #define RT5645_M_ZCD_OM_L (0x1 << 5)
2004 #define RT5645_M_ZCD_OM_R (0x1 << 4)
2009 #define RT5645_ZCD_HP_MASK (0x1 << 15)
2012 #define RT5645_ZCD_HP_EN (0x1 << 15)
2020 #define RT5645_3D_SPK_MASK (0x1 << 15)
2023 #define RT5645_3D_SPK_EN (0x1 << 15)
2032 #define RT5645_WND_MASK (0x1 << 15)
2035 #define RT5645_WND_EN (0x1 << 15)
2058 #define RT5645_WND_WIND_MASK (0x1 << 13) /* Read-Only */
2060 #define RT5645_WND_STRONG_MASK (0x1 << 12) /* Read-Only */
2071 #define RT5645_DP_SPK_MASK (0x1 << 10)
2074 #define RT5645_DP_SPK_EN (0x1 << 10)
2086 #define RT5645_JD_CBJ_EN (0x1 << 7)
2087 #define RT5645_JD_CBJ_POL (0x1 << 6)
2093 #define RT5645_JD_F_JD1_1 (0x1)
2101 #define RT5645_RST_DSP (0x1 << 13)
2102 #define RT5645_IF1_ADC1_IN1_SEL (0x1 << 12)
2104 #define RT5645_IF1_ADC1_IN2_SEL (0x1 << 11)
2106 #define RT5645_IF1_ADC2_IN1_SEL (0x1 << 10)
2108 #define RT5645_DIG_GATE_CTRL 0x1
2111 #define RT5645_RXDC_SRC_MASK (0x1 << 7)
2113 #define RT5645_RXDC_SRC_MONO (0x1 << 7)
2115 #define RT5645_MICBIAS1_POW_CTRL_SEL_MASK (0x1 << 5)
2117 #define RT5645_MICBIAS1_POW_CTRL_SEL_M (0x1 << 5)
2118 #define RT5645_MICBIAS2_POW_CTRL_SEL_MASK (0x1 << 4)
2120 #define RT5645_MICBIAS2_POW_CTRL_SEL_M (0x1 << 4)
2121 #define RT5645_RXDP2_SEL_MASK (0x1 << 3)
2123 #define RT5645_RXDP2_SEL_ADC (0x1 << 3)
2127 #define RT5645_JD_PSV_MODE (0x1 << 12)
2128 #define RT5645_IRQ_CLK_GATE_CTRL (0x1 << 11)
2131 #define RT5645_DET_CLK_MODE1 (0x1 << 9)
2133 #define RT5645_MICINDET_MANU (0x1 << 7)
2134 #define RT5645_RING2_SLEEVE_GND (0x1 << 5)
2190 RT5645_DA_STEREO_FILTER = 0x1,
2191 RT5645_DA_MONO_L_FILTER = (0x1 << 1),
2192 RT5645_DA_MONO_R_FILTER = (0x1 << 2),
2193 RT5645_AD_STEREO_FILTER = (0x1 << 3),
2194 RT5645_AD_MONO_L_FILTER = (0x1 << 4),
2195 RT5645_AD_MONO_R_FILTER = (0x1 << 5),