1 // SPDX-License-Identifier: GPL-2.0-only
3  * rt1305.c  --  RT1305 ALSA SoC amplifier component driver
23 #include <sound/soc-dapm.h>
247 	regmap_multi_reg_write(rt1305->regmap, init_list, RT1305_INIT_REG_LEN);  in rt1305_reg_init()
379 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9435, 37, 0);
404 static int rt1305_is_rc_clk_from_pll(struct snd_soc_dapm_widget *source,  in rt1305_is_rc_clk_from_pll()  argument
408 		snd_soc_dapm_to_component(source->dapm);  in rt1305_is_rc_clk_from_pll()
414 	if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1 &&  in rt1305_is_rc_clk_from_pll()
421 static int rt1305_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,  in rt1305_is_sys_clk_from_pll()  argument
425 		snd_soc_dapm_to_component(source->dapm);  in rt1305_is_sys_clk_from_pll()
428 	if (rt1305->sysclk_src == RT1305_FS_SYS_PRE_S_PLL1)  in rt1305_is_sys_clk_from_pll()
438 		snd_soc_dapm_to_component(w->dapm);  in rt1305_classd_event()
481 	SND_SOC_DAPM_SUPPLY("VREF", RT1305_POWER_CTRL_1,
489 	SND_SOC_DAPM_SUPPLY("DISC VREF", RT1305_POWER_CTRL_2,
491 	SND_SOC_DAPM_SUPPLY("FASTB VREF", RT1305_POWER_CTRL_2,
493 	SND_SOC_DAPM_SUPPLY("ULTRA FAST VREF", RT1305_POWER_CTRL_2,
567 	{ "DAC", NULL, "VREF" },
571 	{ "DAC", NULL, "DISC VREF" },
572 	{ "DAC", NULL, "FASTB VREF" },
573 	{ "DAC", NULL, "ULTRA FAST VREF" },
613 		return -EINVAL;  in rt1305_get_clk_info()
620 	return -EINVAL;  in rt1305_get_clk_info()
626 	struct snd_soc_component *component = dai->component;  in rt1305_hw_params()
631 	rt1305->lrck = params_rate(params);  in rt1305_hw_params()
632 	pre_div = rt1305_get_clk_info(rt1305->sysclk, rt1305->lrck);  in rt1305_hw_params()
634 		dev_warn(component->dev, "Force using PLL ");  in rt1305_hw_params()
636 			rt1305->lrck * 64, rt1305->lrck * 256);  in rt1305_hw_params()
638 			rt1305->lrck * 256, SND_SOC_CLOCK_IN);  in rt1305_hw_params()
643 		dev_err(component->dev, "Unsupported frame size: %d\n",  in rt1305_hw_params()
645 		return -EINVAL;  in rt1305_hw_params()
649 	rt1305->bclk = rt1305->lrck * (32 << bclk_ms);  in rt1305_hw_params()
651 	dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",  in rt1305_hw_params()
652 				bclk_ms, pre_div, dai->id);  in rt1305_hw_params()
654 	dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",  in rt1305_hw_params()
655 				rt1305->lrck, pre_div, dai->id);  in rt1305_hw_params()
671 		return -EINVAL;  in rt1305_hw_params()
674 	switch (dai->id) {  in rt1305_hw_params()
683 		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);  in rt1305_hw_params()
684 		return -EINVAL;  in rt1305_hw_params()
695 	struct snd_soc_component *component = dai->component;  in rt1305_set_dai_fmt()
702 		rt1305->master = 1;  in rt1305_set_dai_fmt()
706 		rt1305->master = 0;  in rt1305_set_dai_fmt()
709 		return -EINVAL;  in rt1305_set_dai_fmt()
719 		return -EINVAL;  in rt1305_set_dai_fmt()
735 		return -EINVAL;  in rt1305_set_dai_fmt()
738 	switch (dai->id) {  in rt1305_set_dai_fmt()
747 		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);  in rt1305_set_dai_fmt()
748 		return -EINVAL;  in rt1305_set_dai_fmt()
754 		int clk_id, int source, unsigned int freq, int dir)  in rt1305_set_component_sysclk()  argument
759 	if (freq == rt1305->sysclk && clk_id == rt1305->sysclk_src)  in rt1305_set_component_sysclk()
776 		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);  in rt1305_set_component_sysclk()
777 		return -EINVAL;  in rt1305_set_component_sysclk()
781 	rt1305->sysclk = freq;  in rt1305_set_component_sysclk()
782 	rt1305->sysclk_src = clk_id;  in rt1305_set_component_sysclk()
784 	dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",  in rt1305_set_component_sysclk()
791 		int pll_id, int source, unsigned int freq_in,  in rt1305_set_component_pll()  argument
798 	if (source == rt1305->pll_src && freq_in == rt1305->pll_in &&  in rt1305_set_component_pll()
799 	    freq_out == rt1305->pll_out)  in rt1305_set_component_pll()
803 		dev_dbg(component->dev, "PLL disabled\n");  in rt1305_set_component_pll()
805 		rt1305->pll_in = 0;  in rt1305_set_component_pll()
806 		rt1305->pll_out = 0;  in rt1305_set_component_pll()
813 	switch (source) {  in rt1305_set_component_pll()
836 		dev_err(component->dev, "Unknown PLL Source %d\n", source);  in rt1305_set_component_pll()
837 		return -EINVAL;  in rt1305_set_component_pll()
842 		dev_err(component->dev, "Unsupported input clock %d\n", freq_in);  in rt1305_set_component_pll()
846 	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",  in rt1305_set_component_pll()
857 	rt1305->pll_in = freq_in;  in rt1305_set_component_pll()
858 	rt1305->pll_out = freq_out;  in rt1305_set_component_pll()
859 	rt1305->pll_src = source;  in rt1305_set_component_pll()
868 	rt1305->component = component;  in rt1305_probe()
880 	rt1305_reset(rt1305->regmap);  in rt1305_remove()
888 	regcache_cache_only(rt1305->regmap, true);  in rt1305_suspend()
889 	regcache_mark_dirty(rt1305->regmap);  in rt1305_suspend()
898 	regcache_cache_only(rt1305->regmap, false);  in rt1305_resume()
899 	regcache_sync(rt1305->regmap);  in rt1305_resume()
920 		.name = "rt1305-aif",
996 	regcache_cache_bypass(rt1305->regmap, true);  in rt1305_calibrate()
998 	rt1305_reset(rt1305->regmap);  in rt1305_calibrate()
999 	regmap_write(rt1305->regmap, RT1305_ADC_SET_3, 0x0219);  in rt1305_calibrate()
1000 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcf, 0x5548);  in rt1305_calibrate()
1001 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);  in rt1305_calibrate()
1002 	regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x1000);  in rt1305_calibrate()
1003 	regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0600);  in rt1305_calibrate()
1004 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xffd0);  in rt1305_calibrate()
1005 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);  in rt1305_calibrate()
1006 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);  in rt1305_calibrate()
1007 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);  in rt1305_calibrate()
1010 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);  in rt1305_calibrate()
1012 	regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0xb000);  in rt1305_calibrate()
1013 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc3, 0xd4a0);  in rt1305_calibrate()
1014 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xcc, 0x00cc);  in rt1305_calibrate()
1015 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xc1, 0x0320);  in rt1305_calibrate()
1016 	regmap_write(rt1305->regmap, RT1305_POWER_STATUS, 0x0000);  in rt1305_calibrate()
1017 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);  in rt1305_calibrate()
1018 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);  in rt1305_calibrate()
1019 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x00c0);  in rt1305_calibrate()
1020 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);  in rt1305_calibrate()
1021 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);  in rt1305_calibrate()
1022 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);  in rt1305_calibrate()
1025 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0080);  in rt1305_calibrate()
1026 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);  in rt1305_calibrate()
1027 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0880);  in rt1305_calibrate()
1028 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfce0);  in rt1305_calibrate()
1029 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfca0);  in rt1305_calibrate()
1030 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfc20);  in rt1305_calibrate()
1031 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x06, 0x0000);  in rt1305_calibrate()
1032 	regmap_write(rt1305->regmap, RT1305_EFUSE_1, 0x0000);  in rt1305_calibrate()
1034 	regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_5, &valmsb);  in rt1305_calibrate()
1035 	regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_6, &vallsb);  in rt1305_calibrate()
1037 	regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_7, &valmsb);  in rt1305_calibrate()
1038 	regmap_read(rt1305->regmap, RT1305_DAC_OFFSET_8, &vallsb);  in rt1305_calibrate()
1043 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x9542);  in rt1305_calibrate()
1044 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0xfcf0);  in rt1305_calibrate()
1045 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0xffff);  in rt1305_calibrate()
1046 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x1dfe);  in rt1305_calibrate()
1047 	regmap_write(rt1305->regmap, RT1305_SILENCE_DETECT, 0x0e13);  in rt1305_calibrate()
1048 	regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0650);  in rt1305_calibrate()
1050 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x50, 0x0064);  in rt1305_calibrate()
1051 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x51, 0x0770);  in rt1305_calibrate()
1052 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x52, 0xc30c);  in rt1305_calibrate()
1053 	regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x8200);  in rt1305_calibrate()
1054 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);  in rt1305_calibrate()
1055 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);  in rt1305_calibrate()
1057 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);  in rt1305_calibrate()
1058 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);  in rt1305_calibrate()
1070 	regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0x9200);  in rt1305_calibrate()
1071 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xfb00);  in rt1305_calibrate()
1072 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xd4, 0xff80);  in rt1305_calibrate()
1074 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x55, &rh);  in rt1305_calibrate()
1075 	regmap_read(rt1305->regmap, RT1305_PR_BASE + 0x56, &rl);  in rt1305_calibrate()
1087 	regmap_write(rt1305->regmap, RT1305_SPK_TEMP_PROTECTION_1, 0xc2ec);  in rt1305_calibrate()
1091 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4e,  in rt1305_calibrate()
1093 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x4f,  in rt1305_calibrate()
1095 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfe,  in rt1305_calibrate()
1097 		regmap_write(rt1305->regmap, RT1305_PR_BASE + 0xfd,  in rt1305_calibrate()
1104 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0dfe);  in rt1305_calibrate()
1106 	regmap_write(rt1305->regmap, RT1305_PR_BASE + 0x5d, 0x0442);  in rt1305_calibrate()
1107 	regmap_write(rt1305->regmap, RT1305_CLOCK_DETECT, 0x3000);  in rt1305_calibrate()
1108 	regmap_write(rt1305->regmap, RT1305_CLK_1, 0x0400);  in rt1305_calibrate()
1109 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_1, 0x0000);  in rt1305_calibrate()
1110 	regmap_write(rt1305->regmap, RT1305_CAL_EFUSE_CLOCK, 0x8000);  in rt1305_calibrate()
1111 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_2, 0x1020);  in rt1305_calibrate()
1112 	regmap_write(rt1305->regmap, RT1305_POWER_CTRL_3, 0x0000);  in rt1305_calibrate()
1114 	regcache_cache_bypass(rt1305->regmap, false);  in rt1305_calibrate()
1123 	rt1305 = devm_kzalloc(&i2c->dev, sizeof(struct rt1305_priv),  in rt1305_i2c_probe()
1126 		return -ENOMEM;  in rt1305_i2c_probe()
1130 	rt1305->regmap = devm_regmap_init_i2c(i2c, &rt1305_regmap);  in rt1305_i2c_probe()
1131 	if (IS_ERR(rt1305->regmap)) {  in rt1305_i2c_probe()
1132 		ret = PTR_ERR(rt1305->regmap);  in rt1305_i2c_probe()
1133 		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",  in rt1305_i2c_probe()
1138 	regmap_read(rt1305->regmap, RT1305_DEVICE_ID, &val);  in rt1305_i2c_probe()
1140 		dev_err(&i2c->dev,  in rt1305_i2c_probe()
1142 		return -ENODEV;  in rt1305_i2c_probe()
1145 	rt1305_reset(rt1305->regmap);  in rt1305_i2c_probe()
1148 	return devm_snd_soc_register_component(&i2c->dev,  in rt1305_i2c_probe()
1157 	rt1305_reset(rt1305->regmap);  in rt1305_i2c_shutdown()