Lines Matching +full:fllao +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
154 dev_dbg(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
169 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
171 struct madera *madera = priv->madera;
176 ret = regmap_read(madera->regmap, w->reg, &val);
178 dev_err(madera->dev, "Failed to check clock source: %d\n", ret);
198 return clk_prepare_enable(madera->mclk[clk_idx].clk);
200 clk_disable_unprepare(madera->mclk[clk_idx].clk);
210 struct madera *madera = priv->madera;
215 if (pm_runtime_suspended(madera->dev))
223 ret = regmap_read(madera->regmap, MADERA_SOFTWARE_RESET, &val);
225 dev_err(madera->dev,
235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
257 ret = regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_15, &val);
259 dev_err(madera->dev, "Failed to read thermal status: %d\n",
273 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
275 struct madera *madera = priv->madera;
286 dev_crit(madera->dev,
288 return -EBUSY;
291 regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
292 1 << w->shift, 1 << w->shift);
295 regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
296 1 << w->shift, 0);
314 dev_crit(madera->dev, "Thermal shutdown\n");
315 ret = regmap_update_bits(madera->regmap,
320 dev_crit(madera->dev,
324 dev_alert(madera->dev, "Thermal warning\n");
326 dev_info(madera->dev, "Spurious thermal warning\n");
335 struct madera *madera = priv->madera;
336 struct device *dev = madera->dev;
357 struct madera *madera = priv->madera;
375 if (n == -EINVAL)
385 return -EINVAL;
400 struct madera *madera = priv->madera;
401 struct madera_codec_pdata *pdata = &madera->pdata.codec;
405 BUILD_BUG_ON(ARRAY_SIZE(pdata->inmode) != MADERA_MAX_INPUT);
406 BUILD_BUG_ON(ARRAY_SIZE(pdata->inmode[0]) != MADERA_MAX_MUXED_CHANNELS);
408 n = madera_get_variable_u32_array(madera->dev, "cirrus,inmode",
417 pdata->inmode[in_idx][ch_idx] = tmp[i];
428 struct madera *madera = priv->madera;
429 struct madera_codec_pdata *pdata = &madera->pdata.codec;
430 u32 out_mono[ARRAY_SIZE(pdata->out_mono)];
435 n = madera_get_variable_u32_array(madera->dev, "cirrus,out-mono",
439 pdata->out_mono[i] = !!out_mono[i];
441 madera_get_variable_u32_array(madera->dev,
442 "cirrus,max-channels-clocked",
443 pdata->max_channels_clocked,
444 ARRAY_SIZE(pdata->max_channels_clocked),
447 madera_get_variable_u32_array(madera->dev, "cirrus,pdm-fmt",
448 pdata->pdm_fmt,
449 ARRAY_SIZE(pdata->pdm_fmt), 1);
451 madera_get_variable_u32_array(madera->dev, "cirrus,pdm-mute",
452 pdata->pdm_mute,
453 ARRAY_SIZE(pdata->pdm_mute), 1);
455 madera_get_variable_u32_array(madera->dev, "cirrus,dmic-ref",
456 pdata->dmic_ref,
457 ARRAY_SIZE(pdata->dmic_ref), 1);
465 BUILD_BUG_ON(!madera_mixer_texts[MADERA_NUM_MIXER_INPUTS - 1]);
466 BUILD_BUG_ON(!madera_mixer_values[MADERA_NUM_MIXER_INPUTS - 1]);
468 if (!dev_get_platdata(priv->madera->dev))
471 mutex_init(&priv->rate_lock);
474 priv->madera->out_clamp[i] = true;
482 mutex_destroy(&priv->rate_lock);
490 struct madera *madera = priv->madera;
493 for (i = 0; i < ARRAY_SIZE(priv->domain_group_ref); ++i)
494 dev_dbg(madera->dev, "domain_grp_ref[%d]=%d\n", i,
495 priv->domain_group_ref[i]);
502 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
504 int dom_grp = w->shift;
506 if (dom_grp >= ARRAY_SIZE(priv->domain_group_ref)) {
508 return -EINVAL;
515 mutex_lock(&priv->rate_lock);
519 dev_dbg(priv->madera->dev, "Inc ref on domain group %d\n",
521 ++priv->domain_group_ref[dom_grp];
524 dev_dbg(priv->madera->dev, "Dec ref on domain group %d\n",
526 --priv->domain_group_ref[dom_grp];
534 mutex_unlock(&priv->rate_lock);
548 struct madera *madera = priv->madera;
549 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
554 if (ucontrol->value.enumerated.item[0] > e->items - 1)
555 return -EINVAL;
557 mux = ucontrol->value.enumerated.item[0];
570 ret = regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1,
573 dev_warn(madera->dev, "Failed to disable outputs: %d\n", ret);
579 if (madera->out_clamp[0])
580 ret = regmap_update_bits(madera->regmap,
584 dev_err(madera->dev, "Failed to set OUT1 demux: %d\n", ret);
587 if (!ep_sel && !madera->pdata.codec.out_mono[0])
594 dev_warn(madera->dev,
603 (madera->out_clamp[0] && !madera->out_shorted[0])) {
604 ret = regmap_update_bits(madera->regmap,
607 madera->hp_ena);
609 dev_warn(madera->dev,
612 else if (madera->hp_ena)
623 dev_err(madera->dev, "Failed to update demux power state: %d\n", ret);
641 ucontrol->value.enumerated.item[0] = val;
655 struct madera *madera = priv->madera;
656 struct regmap *regmap = madera->regmap;
657 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
663 mux = ucontrol->value.enumerated.item[0];
665 return -EINVAL;
667 val = mux << e->shift_l;
668 mask = (e->mask << e->shift_l) | MADERA_IN1L_SRC_SE_MASK;
670 switch (e->reg) {
672 inmode = madera->pdata.codec.inmode[0][2 * mux];
675 inmode = madera->pdata.codec.inmode[0][1 + (2 * mux)];
678 inmode = madera->pdata.codec.inmode[1][2 * mux];
681 inmode = madera->pdata.codec.inmode[1][1 + (2 * mux)];
684 return -EINVAL;
690 dev_dbg(madera->dev, "mux=%u reg=0x%x inmode=0x%x mask=0x%x val=0x%x\n",
691 mux, e->reg, inmode, mask, val);
693 ret = regmap_update_bits_check(regmap, e->reg, mask, val, &changed);
775 count = priv->domain_group_ref[MADERA_DOM_GRP_FX];
779 count = priv->domain_group_ref[MADERA_DOM_GRP_ASRC1];
783 count = priv->domain_group_ref[MADERA_DOM_GRP_ASRC2];
787 count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC1];
791 count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC2];
795 count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC3];
799 count = priv->domain_group_ref[MADERA_DOM_GRP_ISRC4];
802 count = priv->domain_group_ref[MADERA_DOM_GRP_OUT];
805 count = priv->domain_group_ref[MADERA_DOM_GRP_SPD];
809 count = priv->domain_group_ref[MADERA_DOM_GRP_DSP1];
813 count = priv->domain_group_ref[MADERA_DOM_GRP_DSP2];
817 count = priv->domain_group_ref[MADERA_DOM_GRP_DSP3];
821 count = priv->domain_group_ref[MADERA_DOM_GRP_DSP4];
825 count = priv->domain_group_ref[MADERA_DOM_GRP_DSP5];
829 count = priv->domain_group_ref[MADERA_DOM_GRP_DSP6];
833 count = priv->domain_group_ref[MADERA_DOM_GRP_DSP7];
836 count = priv->domain_group_ref[MADERA_DOM_GRP_AIF1];
839 count = priv->domain_group_ref[MADERA_DOM_GRP_AIF2];
842 count = priv->domain_group_ref[MADERA_DOM_GRP_AIF3];
845 count = priv->domain_group_ref[MADERA_DOM_GRP_AIF4];
855 count = priv->domain_group_ref[MADERA_DOM_GRP_SLIMBUS];
858 count = priv->domain_group_ref[MADERA_DOM_GRP_PWM];
864 dev_dbg(priv->madera->dev, "Rate reg 0x%x group ref %d\n", reg, count);
878 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
880 const int adsp_num = e->shift_l;
883 mutex_lock(&priv->rate_lock);
884 cached_rate = priv->adsp_rate_cache[adsp_num];
885 mutex_unlock(&priv->rate_lock);
888 ucontrol->value.enumerated.item[0] = item;
899 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
900 const int adsp_num = e->shift_l;
901 const unsigned int item = ucontrol->value.enumerated.item[0];
904 if (item >= e->items)
905 return -EINVAL;
912 mutex_lock(&priv->rate_lock);
914 if (!madera_can_change_grp_rate(priv, priv->adsp[adsp_num].cs_dsp.base)) {
915 dev_warn(priv->madera->dev,
917 kcontrol->id.name);
918 ret = -EBUSY;
919 } else if (priv->adsp_rate_cache[adsp_num] != e->values[item]) {
921 priv->adsp_rate_cache[adsp_num] = e->values[item];
925 mutex_unlock(&priv->rate_lock);
973 val = priv->adsp_rate_cache[dsp->cs_dsp.num - 1] << MADERA_DSP_RATE_SHIFT;
975 switch (priv->madera->type) {
985 dev_dbg(priv->madera->dev, "Set DSP frequency to 0x%x\n", freq);
987 ret = regmap_write(dsp->cs_dsp.regmap,
988 dsp->cs_dsp.base + MADERA_DSP_CONFIG_2_OFFS, freq);
994 ret = regmap_update_bits(dsp->cs_dsp.regmap,
995 dsp->cs_dsp.base + MADERA_DSP_CONFIG_1_OFFS,
1000 dev_dbg(priv->madera->dev, "Set DSP clocking to 0x%x\n", val);
1005 dev_err(dsp->cs_dsp.dev, "Failed to set DSP%d clock: %d\n", dsp->cs_dsp.num, ret);
1013 struct wm_adsp *dsp = &priv->adsp[dsp_num];
1014 struct madera *madera = priv->madera;
1027 ret = regmap_read(dsp->cs_dsp.regmap, dsp->cs_dsp.base, &cur);
1029 dev_err(madera->dev,
1036 new = priv->adsp_rate_cache[dsp->cs_dsp.num - 1] << MADERA_DSP_RATE_SHIFT;
1039 dev_dbg(madera->dev, "DSP rate not changed\n");
1042 dev_dbg(madera->dev, "DSP rate changed\n");
1059 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1060 unsigned int item = ucontrol->value.enumerated.item[0];
1064 if (item >= e->items)
1065 return -EINVAL;
1071 mutex_lock(&priv->rate_lock);
1073 val = snd_soc_component_read(component, e->reg);
1074 val >>= e->shift_l;
1075 val &= e->mask;
1081 if (!madera_can_change_grp_rate(priv, e->reg)) {
1082 dev_warn(priv->madera->dev,
1084 kcontrol->id.name);
1085 ret = -EBUSY;
1093 mutex_unlock(&priv->rate_lock);
1104 switch (madera->type) {
1134 dev_dbg(madera->dev, "IN%d mode %u:%u:%u:%u\n", i + 1,
1135 madera->pdata.codec.inmode[i][0],
1136 madera->pdata.codec.inmode[i][1],
1137 madera->pdata.codec.inmode[i][2],
1138 madera->pdata.codec.inmode[i][3]);
1140 dig_mode = madera->pdata.codec.dmic_ref[i] <<
1143 switch (madera->pdata.codec.inmode[i][0]) {
1151 dev_warn(madera->dev,
1153 i + 1, madera->pdata.codec.inmode[i][0]);
1157 switch (madera->pdata.codec.inmode[i][1]) {
1165 dev_warn(madera->dev,
1167 i + 1, madera->pdata.codec.inmode[i][1]);
1171 dev_dbg(madera->dev,
1175 regmap_update_bits(madera->regmap,
1182 regmap_update_bits(madera->regmap,
1186 regmap_update_bits(madera->regmap,
1195 struct madera *madera = priv->madera;
1219 struct madera *madera = priv->madera;
1220 const struct madera_codec_pdata *pdata = &madera->pdata.codec;
1225 dev_warn(madera->dev,
1236 if (pdata->out_mono[i]) {
1246 regmap_update_bits(madera->regmap,
1250 dev_dbg(madera->dev, "OUT%d mono=0x%x\n", i + 1, val);
1254 dev_dbg(madera->dev, "PDM%d fmt=0x%x mute=0x%x\n", i + 1,
1255 pdata->pdm_fmt[i], pdata->pdm_mute[i]);
1257 if (pdata->pdm_mute[i])
1258 regmap_update_bits(madera->regmap,
1262 pdata->pdm_mute[i]);
1264 if (pdata->pdm_fmt[i])
1265 regmap_update_bits(madera->regmap,
1268 pdata->pdm_fmt[i]);
1278 struct madera *madera = priv->madera;
1285 &priv->adsp[dsp_num]);
1287 dev_err(madera->dev,
1296 struct madera *madera = priv->madera;
1300 &priv->adsp[dsp_num]);
1611 const DECLARE_TLV_DB_SCALE(madera_eq_tlv, -1200, 100, 0);
1614 const DECLARE_TLV_DB_SCALE(madera_digital_tlv, -6400, 50, 0);
1617 const DECLARE_TLV_DB_SCALE(madera_noise_tlv, -13200, 600, 0);
1620 const DECLARE_TLV_DB_SCALE(madera_ng_tlv, -12000, 600, 0);
1623 const DECLARE_TLV_DB_SCALE(madera_mixer_tlv, -3200, 100, 0);
1994 "Low-pass", "High-pass"
2169 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2170 unsigned int reg = e->reg;
2174 reg = ((reg / 6) * 6) - 2;
2180 ret = -EBUSY;
2181 dev_err(component->dev, "Can't change mode on an active DFC\n");
2197 (struct soc_mixer_control *)kcontrol->private_value;
2209 mask = (mc->reg - MADERA_ADC_DIGITAL_VOLUME_1L) / 4;
2213 ret = -EBUSY;
2214 dev_err(component->dev,
2255 for (i = 0; i < priv->num_inputs; i++) {
2256 ret = regmap_update_bits(priv->madera->regmap,
2260 dev_warn(priv->madera->dev,
2268 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2272 if (w->shift % 2)
2273 reg = MADERA_ADC_DIGITAL_VOLUME_1L + ((w->shift / 2) * 8);
2275 reg = MADERA_ADC_DIGITAL_VOLUME_1R + ((w->shift / 2) * 8);
2279 priv->in_pending++;
2282 priv->in_pending--;
2287 if (priv->in_pending == 0) {
2314 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2316 struct madera *madera = priv->madera;
2319 switch (madera->type) {
2334 switch (w->shift) {
2341 priv->out_up_pending++;
2342 priv->out_up_delay += out_up_delay;
2350 switch (w->shift) {
2357 priv->out_up_pending--;
2358 if (!priv->out_up_pending) {
2359 fsleep(priv->out_up_delay);
2360 priv->out_up_delay = 0;
2370 switch (w->shift) {
2377 priv->out_down_pending++;
2378 priv->out_down_delay += 1000;
2386 switch (w->shift) {
2393 priv->out_down_pending--;
2394 if (!priv->out_down_pending) {
2395 fsleep(priv->out_down_delay);
2396 priv->out_down_delay = 0;
2414 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2416 struct madera *madera = priv->madera;
2417 unsigned int mask = 1 << w->shift;
2418 unsigned int out_num = w->shift / 2;
2437 madera->hp_ena &= ~mask;
2438 madera->hp_ena |= val;
2440 switch (madera->type) {
2447 regmap_read(madera->regmap, MADERA_OUTPUT_ENABLES_1, &ep_sel);
2454 (!madera->out_clamp[out_num] || madera->out_shorted[out_num]))
2457 regmap_update_bits(madera->regmap, MADERA_OUTPUT_ENABLES_1, mask, val);
2466 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2471 val = 1 << w->shift;
2474 val = 1 << (w->shift + 1);
2501 unsigned int clk, unsigned int freq)
2512 switch (clk) {
2515 refclk = priv->sysclk;
2519 refclk = priv->asyncclk;
2522 return -EINVAL;
2537 dev_dbg(component->dev, "Configured %dHz OPCLK\n",
2550 dev_err(component->dev, "Unable to generate %dHz OPCLK\n", freq);
2552 return -EINVAL;
2575 return -EINVAL;
2587 switch (madera->type) {
2590 if (madera->rev < 3)
2591 return -EINVAL;
2596 return -EINVAL;
2602 return -EINVAL;
2610 switch (madera->type) {
2618 return -EINVAL;
2633 dev_dbg(component->dev, "Configured OUTCLK to SYSCLK\n");
2638 dev_dbg(component->dev, "Configured OUTCLK to ASYNCCLK\n");
2647 return -EINVAL;
2659 dev_dbg(component->dev, "Configured %dHz OUTCLK\n", rate);
2672 dev_err(component->dev,
2675 return -EINVAL;
2682 struct madera *madera = priv->madera;
2687 int clk_freq_sel, *clk;
2694 clk = &priv->sysclk;
2701 clk = &priv->asyncclk;
2707 clk = &priv->dspclk;
2717 return -EINVAL;
2721 dev_err(madera->dev,
2722 "Failed to get clk setting for %dHZ\n", freq);
2726 *clk = freq;
2729 dev_dbg(madera->dev, "%s cleared\n", name);
2736 ret = regmap_write(madera->regmap, MADERA_DSP_CLOCK_2,
2739 dev_err(madera->dev,
2754 dev_dbg(madera->dev, "%s set to %uHz\n", name, freq);
2756 return regmap_update_bits(madera->regmap, reg, mask, val);
2762 struct snd_soc_component *component = dai->component;
2764 struct madera *madera = priv->madera;
2767 base = dai->driver->base;
2780 return -EINVAL;
2791 return -EINVAL;
2798 return -EINVAL;
2817 return -EINVAL;
2836 return -EINVAL;
2839 regmap_update_bits(madera->regmap, base + MADERA_AIF_BCLK_CTRL,
2842 regmap_update_bits(madera->regmap, base + MADERA_AIF_TX_PIN_CTRL,
2845 regmap_update_bits(madera->regmap, base + MADERA_AIF_RX_PIN_CTRL,
2848 regmap_update_bits(madera->regmap, base + MADERA_AIF_FORMAT,
2855 -1,
2877 -1,
2942 struct snd_soc_component *component = dai->component;
2944 struct madera_dai_priv *dai_priv = &priv->dai[dai->id - 1];
2945 struct madera *madera = priv->madera;
2948 if (!substream->runtime)
2951 switch (dai_priv->clk) {
2955 base_rate = priv->sysclk;
2959 base_rate = priv->asyncclk;
2965 switch (madera->type) {
2970 dai_priv->constraint.mask = MADERA_384K_RATE_MASK;
2972 dai_priv->constraint.mask = MADERA_384K_44K1_RATE_MASK;
2974 dai_priv->constraint.mask = MADERA_384K_48K_RATE_MASK;
2978 dai_priv->constraint.mask = MADERA_192K_RATE_MASK;
2980 dai_priv->constraint.mask = MADERA_192K_44K1_RATE_MASK;
2982 dai_priv->constraint.mask = MADERA_192K_48K_RATE_MASK;
2986 return snd_pcm_hw_constraint_list(substream->runtime, 0,
2988 &dai_priv->constraint);
2995 struct snd_soc_component *component = dai->component;
2997 struct madera_dai_priv *dai_priv = &priv->dai[dai->id - 1];
2998 int base = dai->driver->base;
3010 return -EINVAL;
3014 switch (dai_priv->clk) {
3036 madera_aif_err(dai, "Invalid clock %d\n", dai_priv->clk);
3037 return -EINVAL;
3046 ret = regmap_read(priv->madera->regmap,
3056 mutex_lock(&priv->rate_lock);
3060 ret = -EBUSY;
3071 mutex_unlock(&priv->rate_lock);
3101 struct snd_soc_component *component = dai->component;
3103 struct madera *madera = priv->madera;
3104 int base = dai->driver->base;
3111 madera->pdata.codec.max_channels_clocked[dai->id - 1];
3112 int tdm_width = priv->tdm_width[dai->id - 1];
3113 int tdm_slots = priv->tdm_slots[dai->id - 1];
3162 return -EINVAL;
3178 regmap_read(madera->regmap, base + MADERA_AIF_TX_ENABLES,
3180 regmap_read(madera->regmap, base + MADERA_AIF_RX_ENABLES,
3183 regmap_update_bits(madera->regmap,
3185 regmap_update_bits(madera->regmap,
3194 regmap_update_bits(madera->regmap,
3197 regmap_update_bits(madera->regmap,
3200 regmap_update_bits(madera->regmap,
3204 regmap_update_bits(madera->regmap,
3213 regmap_update_bits(madera->regmap,
3216 regmap_update_bits(madera->regmap,
3235 return -EINVAL;
3242 struct snd_soc_component *component = dai->component;
3246 struct madera_dai_priv *dai_priv = &priv->dai[dai->id - 1];
3252 dev_err(component->dev, "Illegal DAI clock id %d\n", clk_id);
3256 if (is_sync == madera_is_syncclk(dai_priv->clk))
3260 dev_err(component->dev, "Can't change clock on active DAI %d\n",
3261 dai->id);
3262 return -EBUSY;
3265 dev_dbg(component->dev, "Setting AIF%d to %s\n", dai->id,
3273 routes[0].sink = dai->driver->capture.stream_name;
3274 routes[1].sink = dai->driver->playback.stream_name;
3283 dai_priv->clk = clk_id;
3290 struct snd_soc_component *component = dai->component;
3291 int base = dai->driver->base;
3313 struct snd_soc_component *component = dai->component;
3315 struct madera *madera = priv->madera;
3319 slot = ffs(mask) - 1;
3323 regmap_write(madera->regmap, base + i, slot);
3335 struct snd_soc_component *component = dai->component;
3337 int base = dai->driver->base;
3338 int rx_max_chan = dai->driver->playback.channels_max;
3339 int tx_max_chan = dai->driver->capture.channels_max;
3342 if (dai->id > MADERA_MAX_AIF)
3343 return -ENOTSUPP;
3346 tx_mask = (1 << tx_max_chan) - 1;
3347 rx_mask = (1 << rx_max_chan) - 1;
3355 priv->tdm_width[dai->id - 1] = slot_width;
3356 priv->tdm_slots[dai->id - 1] = slots;
3380 struct madera_dai_priv *dai_priv = &priv->dai[id];
3382 dai_priv->clk = MADERA_CLK_SYSCLK_1;
3383 dai_priv->constraint = madera_constraint;
3429 { 0, 256000, 0, -1 },
3430 { 256000, 1000000, 2, -1 },
3431 { 1000000, 13500000, 4, -1 },
3457 return -EINVAL;
3469 *fratio = ratio - 1;
3477 switch (fll->madera->type) {
3479 switch (fll->madera->rev) {
3488 fll->fout,
3500 return madera_find_main_fratio(fref, fll->fout, fratio);
3513 cfg->refdiv = 0;
3517 cfg->refdiv++;
3520 return -EINVAL;
3524 init_ratio = madera_find_fratio(fll, fref, sync, &cfg->fratio);
3532 cfg->fratio = init_ratio - 1;
3534 switch (fll->madera->type) {
3536 switch (fll->madera->rev) {
3558 refdiv = cfg->refdiv;
3565 for (ratio = init_ratio; ratio > 0; ratio--) {
3566 if (fll->fout % (ratio * fref)) {
3567 cfg->refdiv = refdiv;
3568 cfg->fratio = ratio - 1;
3579 if (fref > pseudo_fref_max[ratio - 1])
3582 if (fll->fout % (ratio * fref)) {
3583 cfg->refdiv = refdiv;
3584 cfg->fratio = ratio - 1;
3597 return cfg->fratio + 1;
3610 cfg->gain = gains[i].gain;
3611 cfg->alt_gain = gains[i].alt_gain;
3618 return -EINVAL;
3631 fref, fll->fout, fll->fout * MADERA_FLL_VCO_MULT);
3639 fref = fref / (1 << cfg->refdiv);
3641 cfg->n = fll->fout / (ratio * fref);
3643 if (fll->fout % (ratio * fref)) {
3644 gcd_fll = gcd(fll->fout, ratio * fref);
3647 cfg->theta = (fll->fout - (cfg->n * ratio * fref))
3649 cfg->lambda = (ratio * fref) / gcd_fll;
3651 cfg->theta = 0;
3652 cfg->lambda = 0;
3660 while (cfg->lambda >= (1 << 16)) {
3661 cfg->theta >>= 1;
3662 cfg->lambda >>= 1;
3665 switch (fll->madera->type) {
3667 switch (fll->madera->rev) {
3706 cfg->n, cfg->theta, cfg->lambda);
3708 cfg->fratio, ratio, cfg->refdiv, 1 << cfg->refdiv);
3709 madera_fll_dbg(fll, "GAIN=0x%x(%d)\n", cfg->gain, 1 << cfg->gain);
3721 regmap_update_bits_check(madera->regmap,
3724 cfg->theta, &change);
3726 regmap_update_bits_check(madera->regmap,
3729 cfg->lambda, &change);
3731 regmap_update_bits_check(madera->regmap,
3734 cfg->fratio << MADERA_FLL1_FRATIO_SHIFT,
3737 regmap_update_bits_check(madera->regmap,
3741 cfg->refdiv << MADERA_FLL1_REFCLK_DIV_SHIFT |
3747 regmap_update_bits_check(madera->regmap,
3754 regmap_update_bits_check(madera->regmap,
3762 regmap_update_bits_check(madera->regmap,
3765 MADERA_FLL1_CTRL_UPD | cfg->n, &change);
3773 struct madera *madera = fll->madera;
3777 ret = regmap_read(madera->regmap,
3789 struct madera *madera = fll->madera;
3797 regmap_read(madera->regmap, MADERA_IRQ1_RAW_STATUS_2, &val);
3798 status = val & (MADERA_FLL1_LOCK_STS1 << (fll->id - 1));
3817 return -ETIMEDOUT;
3827 if (!sync && ref_cfg->theta == 0)
3833 regmap_update_bits_check(fll->madera->regmap,
3834 fll->base + MADERA_FLL_EFS_2_OFFS,
3846 struct madera *madera = fll->madera;
3848 struct clk *clk;
3851 ret = regmap_read(madera->regmap, reg, &src);
3862 clk = madera->mclk[MADERA_MCLK1].clk;
3865 clk = madera->mclk[MADERA_MCLK2].clk;
3868 clk = madera->mclk[MADERA_MCLK3].clk;
3875 return clk_prepare_enable(clk);
3877 clk_disable_unprepare(clk);
3908 struct madera *madera = fll->madera;
3912 switch (madera->type) {
3914 sync_base = fll->base + CS47L35_FLL_SYNCHRONISER_OFFS;
3917 sync_base = fll->base + MADERA_FLL_SYNCHRONISER_OFFS;
3923 regmap_update_bits(madera->regmap,
3924 fll->base + MADERA_FLL_CONTROL_1_OFFS,
3926 regmap_update_bits_check(madera->regmap,
3927 fll->base + MADERA_FLL_CONTROL_1_OFFS,
3929 regmap_update_bits_check(madera->regmap,
3932 regmap_update_bits(madera->regmap,
3933 fll->base + MADERA_FLL_CONTROL_1_OFFS,
3942 madera_set_fll_clks(fll, fll->base, false);
3943 pm_runtime_put_autosuspend(madera->dev);
3949 struct madera *madera = fll->madera;
3951 int already_enabled = madera_is_enabled_fll(fll, fll->base);
3961 if (fll->ref_src < 0 || fll->ref_freq == 0) {
3963 ret = -EINVAL;
3970 if (fll->fout < MADERA_FLL_MIN_FOUT ||
3971 fll->fout > MADERA_FLL_MAX_FOUT) {
3972 madera_fll_err(fll, "invalid fout %uHz\n", fll->fout);
3973 ret = -EINVAL;
3977 switch (madera->type) {
3979 sync_base = fll->base + CS47L35_FLL_SYNCHRONISER_OFFS;
3982 sync_base = fll->base + MADERA_FLL_SYNCHRONISER_OFFS;
3992 regmap_update_bits(fll->madera->regmap,
3993 fll->base + MADERA_FLL_CONTROL_1_OFFS,
3997 regmap_update_bits(fll->madera->regmap,
3998 fll->base + MADERA_FLL_CONTROL_7_OFFS,
4003 madera_set_fll_clks(fll, fll->base, false);
4007 if (fll->sync_src >= 0) {
4008 ret = madera_calc_fll(fll, &cfg, fll->sync_freq, true);
4013 &cfg, fll->sync_src,
4022 ret = madera_calc_fll(fll, &cfg, fll->ref_freq, false);
4030 switch (fll->madera->type) {
4032 switch (fll->madera->rev) {
4061 fll_change |= madera_write_fll(madera, fll->base,
4062 &cfg, fll->ref_src,
4069 if (have_sync && fll->sync_freq > 100000)
4070 regmap_update_bits(madera->regmap,
4074 regmap_update_bits(madera->regmap,
4080 pm_runtime_get_sync(madera->dev);
4084 regmap_update_bits(madera->regmap,
4090 madera_set_fll_clks(fll, fll->base, true);
4091 regmap_update_bits(madera->regmap,
4092 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4096 regmap_update_bits(madera->regmap,
4097 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4114 if (fll->fout) {
4131 if (fll->sync_src == source && fll->sync_freq == fref)
4134 fll->sync_src = source;
4135 fll->sync_freq = fref;
4146 if (fll->ref_src == source &&
4147 fll->ref_freq == fref && fll->fout == fout)
4154 if (fout && fout != fll->fout) {
4155 ret = madera_is_enabled_fll(fll, fll->base);
4161 return -EBUSY;
4165 fll->ref_src = source;
4166 fll->ref_freq = fref;
4167 fll->fout = fout;
4176 fll->id = id;
4177 fll->base = base;
4178 fll->madera = madera;
4179 fll->ref_src = MADERA_FLL_SRC_NONE;
4180 fll->sync_src = MADERA_FLL_SRC_NONE;
4182 regmap_update_bits(madera->regmap,
4183 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4243 struct madera *madera = fll->madera;
4244 int already_enabled = madera_is_enabled_fll(fll, fll->base);
4252 pm_runtime_get_sync(madera->dev);
4258 regmap_update_bits(fll->madera->regmap,
4259 fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
4263 madera_set_fllao_clks(fll, fll->base, false);
4268 /* modify the patch to apply fll->ref_src as input clock */
4271 val |= (fll->ref_src << MADERA_FLL_AO_REFCLK_SRC_SHIFT)
4275 regmap_write(madera->regmap, patch[i].reg, val);
4278 madera_set_fllao_clks(fll, fll->base, true);
4280 regmap_update_bits(madera->regmap,
4281 fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
4285 regmap_update_bits(madera->regmap,
4286 fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
4297 struct madera *madera = fll->madera;
4302 regmap_update_bits(madera->regmap,
4303 fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
4305 regmap_update_bits_check(madera->regmap,
4306 fll->base + MADERA_FLLAO_CONTROL_1_OFFS,
4314 * enables the fllao then ctrl_up is the last bit that is configured
4315 * by the fllao enable code rather than the cache sync operation which
4316 * would have updated it much earlier before writing out all fllao
4319 regmap_update_bits(madera->regmap,
4320 fll->base + MADERA_FLLAO_CONTROL_2_OFFS,
4324 madera_set_fllao_clks(fll, fll->base, false);
4325 pm_runtime_put_autosuspend(madera->dev);
4339 if (fll->ref_src == source &&
4340 fll->ref_freq == fin && fll->fout == fout)
4346 if (fout && (fll->ref_freq != fin || fll->fout != fout)) {
4356 return -EINVAL;
4363 fll->ref_src = source;
4364 fll->ref_freq = fin;
4365 fll->fout = fout;
4378 struct madera *madera = fll->madera;
4385 * again due to a control clock being required, the lock won't re-assert
4389 regmap_update_bits(madera->regmap,
4390 fll->base + MADERA_FLL_CONTROL_11_OFFS,
4392 regmap_update_bits(madera->regmap,
4393 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4395 regmap_update_bits_check(madera->regmap,
4396 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4408 regmap_update_bits(madera->regmap,
4409 fll->base + MADERA_FLL_CONTROL_2_OFFS,
4413 madera_set_fllhj_clks(fll, fll->base, false);
4414 pm_runtime_put_autosuspend(madera->dev);
4422 struct madera *madera = fll->madera;
4428 madera_fll_dbg(fll, "fin=%d, fout=%d\n", fin, fll->fout);
4440 fout = fll->fout;
4463 fout = fll->fout * 6;
4486 return -EINVAL;
4493 return -EINVAL;
4512 madera_fll_err(fll, "N not in valid %s mode range %d-%d: %d\n",
4515 return -EINVAL;
4520 return -EINVAL;
4524 regmap_write(madera->regmap,
4525 fll->base + MADERA_FLL_CONTROL_2_OFFS,
4527 regmap_update_bits(madera->regmap,
4528 fll->base + MADERA_FLL_CONTROL_3_OFFS,
4531 regmap_update_bits(madera->regmap,
4532 fll->base + MADERA_FLL_CONTROL_4_OFFS,
4535 regmap_update_bits(madera->regmap,
4536 fll->base + MADERA_FLL_CONTROL_5_OFFS,
4539 regmap_update_bits(madera->regmap,
4540 fll->base + MADERA_FLL_CONTROL_6_OFFS,
4543 regmap_update_bits(madera->regmap,
4544 fll->base + MADERA_FLL_GAIN_OFFS,
4549 regmap_update_bits(madera->regmap,
4550 fll->base + MADERA_FLL_CONTROL_10_OFFS,
4553 regmap_update_bits(madera->regmap,
4554 fll->base + MADERA_FLL_CONTROL_11_OFFS,
4557 regmap_update_bits(madera->regmap,
4558 fll->base + MADERA_FLL1_DIGITAL_TEST_1_OFFS,
4568 struct madera *madera = fll->madera;
4569 int already_enabled = madera_is_enabled_fll(fll, fll->base);
4576 pm_runtime_get_sync(madera->dev);
4582 regmap_update_bits(fll->madera->regmap,
4583 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4588 madera_set_fllhj_clks(fll, fll->base, false);
4591 ret = madera_fllhj_apply(fll, fll->ref_freq);
4596 regmap_update_bits(madera->regmap,
4597 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4599 fll->ref_src << CS47L92_FLL1_REFCLK_SRC_SHIFT);
4601 madera_set_fllhj_clks(fll, fll->base, true);
4603 regmap_update_bits(madera->regmap,
4604 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4609 regmap_update_bits(madera->regmap,
4610 fll->base + MADERA_FLL_CONTROL_11_OFFS,
4614 regmap_update_bits(madera->regmap,
4615 fll->base + MADERA_FLL_CONTROL_2_OFFS,
4620 regmap_update_bits(madera->regmap,
4621 fll->base + MADERA_FLL_CONTROL_1_OFFS,
4636 madera_fll_err(fll, "fllout set without valid input clk\n");
4637 return -EINVAL;
4640 if (fll->fout && fout != fll->fout) {
4642 return -EINVAL;
4647 return -EINVAL;
4665 if (fll->ref_src == source && fll->ref_freq == fin &&
4666 fll->fout == fout)
4670 return -EINVAL;
4672 fll->ref_src = source;
4673 fll->ref_freq = fin;
4674 fll->fout = fout;
4686 * madera_set_output_mode - Set the mode of the specified output
4708 return -EINVAL;
4710 reg = MADERA_OUTPUT_PATH_CONFIG_1L + (output - 1) * 8;
4737 return (abs((a << 16) / (4096 - b)) >= 4096 << 4);
4747 struct madera *madera = priv->madera;
4748 struct soc_bytes *params = (void *)kcontrol->private_value;
4754 len = params->num_regs * regmap_get_val_bytes(madera->regmap);
4756 data = kmemdup(ucontrol->value.bytes.data, len, GFP_KERNEL | GFP_DMA);
4758 return -ENOMEM;
4767 dev_err(madera->dev, "Rejecting unstable EQ coefficients\n");
4768 ret = -EINVAL;
4772 ret = regmap_read(madera->regmap, params->base, &val);
4779 ret = regmap_raw_write(madera->regmap, params->base, data, len);
4794 struct madera *madera = priv->madera;
4795 __be16 *data = (__be16 *)ucontrol->value.bytes.data;
4799 dev_err(madera->dev, "Rejecting unstable LHPF coefficients\n");
4800 return -EINVAL;