Lines Matching full:tx
244 struct tx_macro *tx; member
250 struct tx_macro *tx; member
284 /* TX Macro */
428 /* Update volatile list for tx/tx macros */ in tx_is_volatile_register()
601 static int tx_macro_mclk_enable(struct tx_macro *tx, in tx_macro_mclk_enable() argument
604 struct regmap *regmap = tx->regmap; in tx_macro_mclk_enable()
607 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
619 tx->tx_mclk_users++; in tx_macro_mclk_enable()
621 if (tx->tx_mclk_users <= 0) { in tx_macro_mclk_enable()
622 dev_err(tx->dev, "clock already disabled\n"); in tx_macro_mclk_enable()
623 tx->tx_mclk_users = 0; in tx_macro_mclk_enable()
626 tx->tx_mclk_users--; in tx_macro_mclk_enable()
627 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
659 struct tx_macro *tx; in tx_macro_tx_hpf_corner_freq_callback() local
666 tx = hpf_work->tx; in tx_macro_tx_hpf_corner_freq_callback()
667 component = tx->component; in tx_macro_tx_hpf_corner_freq_callback()
703 struct tx_macro *tx; in tx_macro_mute_update_callback() local
709 tx = tx_mute_dwork->tx; in tx_macro_mute_update_callback()
710 component = tx->component; in tx_macro_mute_update_callback()
721 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_mclk_event() local
725 tx_macro_mclk_enable(tx, true); in tx_macro_mclk_event()
728 tx_macro_mclk_enable(tx, false); in tx_macro_mclk_event()
746 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_put_dec_enum() local
796 tx->dmic_clk_div); in tx_macro_put_dec_enum()
811 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_tx_mixer_get() local
813 if (test_bit(dec_id, &tx->active_ch_mask[dai_id])) in tx_macro_tx_mixer_get()
831 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_tx_mixer_put() local
834 if (tx->active_decimator[dai_id] == dec_id) in tx_macro_tx_mixer_put()
837 set_bit(dec_id, &tx->active_ch_mask[dai_id]); in tx_macro_tx_mixer_put()
838 tx->active_ch_cnt[dai_id]++; in tx_macro_tx_mixer_put()
839 tx->active_decimator[dai_id] = dec_id; in tx_macro_tx_mixer_put()
841 if (tx->active_decimator[dai_id] == -1) in tx_macro_tx_mixer_put()
844 tx->active_ch_cnt[dai_id]--; in tx_macro_tx_mixer_put()
845 clear_bit(dec_id, &tx->active_ch_mask[dai_id]); in tx_macro_tx_mixer_put()
846 tx->active_decimator[dai_id] = -1; in tx_macro_tx_mixer_put()
864 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_enable_dec() local
885 tx->dmic_clk_div); in tx_macro_enable_dec()
890 tx->dec_mode[decimator]); in tx_macro_enable_dec()
891 /* Enable TX PGA Mute */ in tx_macro_enable_dec()
906 tx->tx_hpf_work[decimator].hpf_cut_off_freq = in tx_macro_enable_dec()
920 &tx->tx_mute_dwork[decimator].dwork, in tx_macro_enable_dec()
922 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) { in tx_macro_enable_dec()
924 &tx->tx_hpf_work[decimator].dwork, in tx_macro_enable_dec()
949 if (tx->bcs_enable) { in tx_macro_enable_dec()
952 tx->bcs_clk_en = true; in tx_macro_enable_dec()
957 tx->tx_hpf_work[decimator].hpf_cut_off_freq; in tx_macro_enable_dec()
961 &tx->tx_hpf_work[decimator].dwork)) { in tx_macro_enable_dec()
991 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); in tx_macro_enable_dec()
1000 if (tx->bcs_enable) { in tx_macro_enable_dec()
1007 tx->bcs_clk_en = false; in tx_macro_enable_dec()
1018 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_dec_mode_get() local
1022 ucontrol->value.integer.value[0] = tx->dec_mode[path]; in tx_macro_dec_mode_get()
1034 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_dec_mode_put() local
1036 if (tx->dec_mode[path] == value) in tx_macro_dec_mode_put()
1039 tx->dec_mode[path] = value; in tx_macro_dec_mode_put()
1048 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_get_bcs() local
1050 ucontrol->value.integer.value[0] = tx->bcs_enable; in tx_macro_get_bcs()
1060 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_set_bcs() local
1062 tx->bcs_enable = value; in tx_macro_set_bcs()
1075 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_hw_params() local
1101 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", in tx_macro_hw_params()
1106 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX) in tx_macro_hw_params()
1118 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_get_channel_map() local
1124 *tx_slot = tx->active_ch_mask[dai->id]; in tx_macro_get_channel_map()
1125 *tx_num = tx->active_ch_cnt[dai->id]; in tx_macro_get_channel_map()
1136 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_digital_mute() local
1140 if (tx->active_decimator[dai->id] == -1) in tx_macro_digital_mute()
1143 decimator = tx->active_decimator[dai->id]; in tx_macro_digital_mute()
1430 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1431 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1432 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1433 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1434 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1435 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1436 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1437 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1439 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
1440 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
1441 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
1442 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
1443 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
1444 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
1445 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
1446 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
1448 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1449 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1450 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1451 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1452 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1453 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1454 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1455 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1456 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1457 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1458 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1459 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1460 SND_SOC_DAPM_INPUT("TX DMIC0"),
1461 SND_SOC_DAPM_INPUT("TX DMIC1"),
1462 SND_SOC_DAPM_INPUT("TX DMIC2"),
1463 SND_SOC_DAPM_INPUT("TX DMIC3"),
1464 SND_SOC_DAPM_INPUT("TX DMIC4"),
1465 SND_SOC_DAPM_INPUT("TX DMIC5"),
1466 SND_SOC_DAPM_INPUT("TX DMIC6"),
1467 SND_SOC_DAPM_INPUT("TX DMIC7"),
1469 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1475 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1481 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1487 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1493 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1499 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1505 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1511 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1535 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1536 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1537 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1538 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1539 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1540 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1541 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1542 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1544 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1545 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1546 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1547 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1548 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1549 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1550 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1551 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1553 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1554 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1555 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1556 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1557 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1558 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1559 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1560 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1562 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1563 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1564 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1565 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1566 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1567 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1568 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1569 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1571 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
1572 {"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
1573 {"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
1574 {"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
1575 {"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
1576 {"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
1577 {"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
1578 {"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
1579 {"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
1581 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1582 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1583 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1584 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1585 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1586 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1587 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1588 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1589 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1590 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1591 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1592 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1593 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1594 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1596 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
1597 {"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
1598 {"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
1599 {"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
1600 {"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
1601 {"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
1602 {"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
1603 {"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
1604 {"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
1606 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1607 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1608 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1609 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1610 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1611 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1612 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1613 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1614 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1615 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1616 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1617 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1618 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1619 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1621 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
1622 {"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
1623 {"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
1624 {"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
1625 {"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
1626 {"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
1627 {"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
1628 {"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
1629 {"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
1631 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1632 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1633 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1634 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1635 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1636 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1637 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1638 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1639 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1640 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1641 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1642 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1643 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1644 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1646 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
1647 {"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
1648 {"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
1649 {"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
1650 {"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
1651 {"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
1652 {"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
1653 {"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
1654 {"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
1656 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1657 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1658 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1659 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1660 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1661 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1662 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1663 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1664 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1665 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1666 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1667 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1668 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1669 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1671 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
1672 {"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
1673 {"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
1674 {"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
1675 {"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
1676 {"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
1677 {"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
1678 {"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
1679 {"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
1681 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1682 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1683 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1684 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1685 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1686 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1687 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1688 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1689 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1690 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1691 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1692 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1693 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1694 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1696 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
1697 {"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
1698 {"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
1699 {"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
1700 {"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
1701 {"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
1702 {"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
1703 {"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
1704 {"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
1706 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1707 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1708 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1709 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1710 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1711 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1712 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1713 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1714 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1715 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1716 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1717 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1718 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1719 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1721 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
1722 {"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
1723 {"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
1724 {"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
1725 {"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
1726 {"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
1727 {"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
1728 {"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
1729 {"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
1731 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1732 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1733 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1734 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1735 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1736 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1737 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1738 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1739 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1740 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1741 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1742 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1743 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1744 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1746 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
1747 {"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
1748 {"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
1749 {"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
1750 {"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
1751 {"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
1752 {"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
1753 {"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
1754 {"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
1756 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1757 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1758 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1759 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1760 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1761 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1762 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1763 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1764 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1765 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1766 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1767 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1768 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1769 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1828 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); in tx_macro_component_probe() local
1831 snd_soc_component_init_regmap(comp, tx->regmap); in tx_macro_component_probe()
1834 tx->tx_hpf_work[i].tx = tx; in tx_macro_component_probe()
1835 tx->tx_hpf_work[i].decimator = i; in tx_macro_component_probe()
1836 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork, in tx_macro_component_probe()
1841 tx->tx_mute_dwork[i].tx = tx; in tx_macro_component_probe()
1842 tx->tx_mute_dwork[i].decimator = i; in tx_macro_component_probe()
1843 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork, in tx_macro_component_probe()
1846 tx->component = comp; in tx_macro_component_probe()
1859 struct tx_macro *tx = to_tx_macro(hw); in swclk_gate_enable() local
1860 struct regmap *regmap = tx->regmap; in swclk_gate_enable()
1863 ret = clk_prepare_enable(tx->mclk); in swclk_gate_enable()
1865 dev_err(tx->dev, "failed to enable mclk\n"); in swclk_gate_enable()
1869 tx_macro_mclk_enable(tx, true); in swclk_gate_enable()
1879 struct tx_macro *tx = to_tx_macro(hw); in swclk_gate_disable() local
1880 struct regmap *regmap = tx->regmap; in swclk_gate_disable()
1885 tx_macro_mclk_enable(tx, false); in swclk_gate_disable()
1886 clk_disable_unprepare(tx->mclk); in swclk_gate_disable()
1891 struct tx_macro *tx = to_tx_macro(hw); in swclk_gate_is_enabled() local
1894 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
1914 static int tx_macro_register_mclk_output(struct tx_macro *tx) in tx_macro_register_mclk_output() argument
1916 struct device *dev = tx->dev; in tx_macro_register_mclk_output()
1918 const char *clk_name = "lpass-tx-mclk"; in tx_macro_register_mclk_output()
1923 if (tx->npl) in tx_macro_register_mclk_output()
1924 parent_clk_name = __clk_get_name(tx->npl); in tx_macro_register_mclk_output()
1926 parent_clk_name = __clk_get_name(tx->mclk); in tx_macro_register_mclk_output()
1933 tx->hw.init = &init; in tx_macro_register_mclk_output()
1934 hw = &tx->hw; in tx_macro_register_mclk_output()
1958 struct tx_macro *tx; in tx_macro_probe() local
1964 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL); in tx_macro_probe()
1965 if (!tx) in tx_macro_probe()
1968 tx->macro = devm_clk_get_optional(dev, "macro"); in tx_macro_probe()
1969 if (IS_ERR(tx->macro)) in tx_macro_probe()
1970 return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n"); in tx_macro_probe()
1972 tx->dcodec = devm_clk_get_optional(dev, "dcodec"); in tx_macro_probe()
1973 if (IS_ERR(tx->dcodec)) in tx_macro_probe()
1974 return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n"); in tx_macro_probe()
1976 tx->mclk = devm_clk_get(dev, "mclk"); in tx_macro_probe()
1977 if (IS_ERR(tx->mclk)) in tx_macro_probe()
1978 return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n"); in tx_macro_probe()
1981 tx->npl = devm_clk_get(dev, "npl"); in tx_macro_probe()
1982 if (IS_ERR(tx->npl)) in tx_macro_probe()
1983 return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n"); in tx_macro_probe()
1986 tx->fsgen = devm_clk_get(dev, "fsgen"); in tx_macro_probe()
1987 if (IS_ERR(tx->fsgen)) in tx_macro_probe()
1988 return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n"); in tx_macro_probe()
1990 tx->pds = lpass_macro_pds_init(dev); in tx_macro_probe()
1991 if (IS_ERR(tx->pds)) in tx_macro_probe()
1992 return PTR_ERR(tx->pds); in tx_macro_probe()
2001 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) { in tx_macro_probe()
2014 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); in tx_macro_probe()
2015 if (IS_ERR(tx->regmap)) { in tx_macro_probe()
2016 ret = PTR_ERR(tx->regmap); in tx_macro_probe()
2020 dev_set_drvdata(dev, tx); in tx_macro_probe()
2022 tx->dev = dev; in tx_macro_probe()
2025 tx->active_decimator[TX_MACRO_AIF1_CAP] = -1; in tx_macro_probe()
2026 tx->active_decimator[TX_MACRO_AIF2_CAP] = -1; in tx_macro_probe()
2027 tx->active_decimator[TX_MACRO_AIF3_CAP] = -1; in tx_macro_probe()
2030 clk_set_rate(tx->mclk, MCLK_FREQ); in tx_macro_probe()
2031 clk_set_rate(tx->npl, MCLK_FREQ); in tx_macro_probe()
2033 ret = clk_prepare_enable(tx->macro); in tx_macro_probe()
2037 ret = clk_prepare_enable(tx->dcodec); in tx_macro_probe()
2041 ret = clk_prepare_enable(tx->mclk); in tx_macro_probe()
2045 ret = clk_prepare_enable(tx->npl); in tx_macro_probe()
2049 ret = clk_prepare_enable(tx->fsgen); in tx_macro_probe()
2054 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2057 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2060 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2075 ret = tx_macro_register_mclk_output(tx); in tx_macro_probe()
2082 clk_disable_unprepare(tx->fsgen); in tx_macro_probe()
2084 clk_disable_unprepare(tx->npl); in tx_macro_probe()
2086 clk_disable_unprepare(tx->mclk); in tx_macro_probe()
2088 clk_disable_unprepare(tx->dcodec); in tx_macro_probe()
2090 clk_disable_unprepare(tx->macro); in tx_macro_probe()
2092 lpass_macro_pds_exit(tx->pds); in tx_macro_probe()
2099 struct tx_macro *tx = dev_get_drvdata(&pdev->dev); in tx_macro_remove() local
2101 clk_disable_unprepare(tx->macro); in tx_macro_remove()
2102 clk_disable_unprepare(tx->dcodec); in tx_macro_remove()
2103 clk_disable_unprepare(tx->mclk); in tx_macro_remove()
2104 clk_disable_unprepare(tx->npl); in tx_macro_remove()
2105 clk_disable_unprepare(tx->fsgen); in tx_macro_remove()
2107 lpass_macro_pds_exit(tx->pds); in tx_macro_remove()
2112 struct tx_macro *tx = dev_get_drvdata(dev); in tx_macro_runtime_suspend() local
2114 regcache_cache_only(tx->regmap, true); in tx_macro_runtime_suspend()
2115 regcache_mark_dirty(tx->regmap); in tx_macro_runtime_suspend()
2117 clk_disable_unprepare(tx->fsgen); in tx_macro_runtime_suspend()
2118 clk_disable_unprepare(tx->npl); in tx_macro_runtime_suspend()
2119 clk_disable_unprepare(tx->mclk); in tx_macro_runtime_suspend()
2126 struct tx_macro *tx = dev_get_drvdata(dev); in tx_macro_runtime_resume() local
2129 ret = clk_prepare_enable(tx->mclk); in tx_macro_runtime_resume()
2135 ret = clk_prepare_enable(tx->npl); in tx_macro_runtime_resume()
2141 ret = clk_prepare_enable(tx->fsgen); in tx_macro_runtime_resume()
2147 regcache_cache_only(tx->regmap, false); in tx_macro_runtime_resume()
2148 regcache_sync(tx->regmap); in tx_macro_runtime_resume()
2152 clk_disable_unprepare(tx->npl); in tx_macro_runtime_resume()
2154 clk_disable_unprepare(tx->mclk); in tx_macro_runtime_resume()
2165 .compatible = "qcom,sc7280-lpass-tx-macro",
2168 .compatible = "qcom,sm8250-lpass-tx-macro",
2171 .compatible = "qcom,sm8450-lpass-tx-macro",
2174 .compatible = "qcom,sm8550-lpass-tx-macro",
2176 .compatible = "qcom,sc8280xp-lpass-tx-macro",
2195 MODULE_DESCRIPTION("TX macro driver");