Lines Matching +full:5 +full:db

35 #define INNO_R01_PINDIR_MSK		(0x1 << 5)
36 #define INNO_R01_PINDIR_IN_SLAVE	(0x0 << 5) /*direction of pin*/
37 #define INNO_R01_PINDIR_OUT_MASTER	(0x1 << 5)
47 #define INNO_R02_VWL_MSK		(0x3 << 5)
48 #define INNO_R02_VWL_32BIT		(0x3 << 5) /*1/2Frame Valid Word Len*/
49 #define INNO_R02_VWL_24BIT		(0x2 << 5)
50 #define INNO_R02_VWL_20BIT		(0x1 << 5)
51 #define INNO_R02_VWL_16BIT		(0x0 << 5)
73 #define INNO_R04_DACL_VREF_SHIFT	5
84 #define INNO_R06_DAC_EN_SHIFT		5
90 /* Gain of output, 1.5db step: -39db(0x0) ~ 0db(0x1a) ~ 6db(0x1f) */
100 #define INNO_R09_HPL_MUTE_SHIFT		5
114 #define INNO_R10_CHARGE_SEL_CUR_027I_YES	(0x0 << 5)
115 #define INNO_R10_CHARGE_SEL_CUR_027I_NO		(0x1 << 5)