Lines Matching +full:left +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * es8328.c -- ES8328 ALSA SoC Audio driver
5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD
100 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
101 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
102 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
124 if (es8328->deemph) { in es8328_set_deemph()
127 if (abs(deemph_settings[i].rate - es8328->playback_fs) < in es8328_set_deemph()
128 abs(deemph_settings[best].rate - es8328->playback_fs)) in es8328_set_deemph()
137 dev_dbg(component->dev, "Set deemphasis %d\n", val); in es8328_set_deemph()
149 ucontrol->value.integer.value[0] = es8328->deemph; in es8328_get_deemph()
158 unsigned int deemph = ucontrol->value.integer.value[0]; in es8328_put_deemph()
162 return -EINVAL; in es8328_put_deemph()
164 if (es8328->deemph == deemph) in es8328_put_deemph()
171 es8328->deemph = deemph; in es8328_put_deemph()
189 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
191 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
193 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
235 /* Left Mixer */
237 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
244 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
245 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
252 /* Left PGA Mux */
276 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
286 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
291 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
298 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
305 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
335 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
338 SND_SOC_DAPM_MIXER("Left Mixer", ES8328_DACCONTROL17, 7, 0,
347 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
351 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
367 { "Left Line Mux", "Line 1", "LINPUT1" },
368 { "Left Line Mux", "Line 2", "LINPUT2" },
369 { "Left Line Mux", "PGA", "Left PGA Mux" },
370 { "Left Line Mux", "Differential", "Differential Mux" },
377 { "Left PGA Mux", "Line 1", "LINPUT1" },
378 { "Left PGA Mux", "Line 2", "LINPUT2" },
379 { "Left PGA Mux", "Differential", "Differential Mux" },
390 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
391 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
392 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
398 { "Left ADC", NULL, "Left ADC Mux" },
405 { "Left ADC", NULL, "ADC DIG" },
410 { "Left Line Mux", "Line 1", "LINPUT1" },
411 { "Left Line Mux", "Line 2", "LINPUT2" },
412 { "Left Line Mux", "PGA", "Left PGA Mux" },
413 { "Left Line Mux", "Differential", "Differential Mux" },
420 { "Left Mixer", NULL, "Left DAC" },
421 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
422 { "Left Mixer", "Right Playback Switch", "Right DAC" },
423 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
425 { "Right Mixer", "Left Playback Switch", "Left DAC" },
426 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
434 { "Left DAC", NULL, "DAC DIG" },
437 { "Left Out 1", NULL, "Left Mixer" },
438 { "LOUT1", NULL, "Left Out 1" },
442 { "Left Out 2", NULL, "Left Mixer" },
443 { "LOUT2", NULL, "Left Out 2" },
450 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, in es8328_mute()
458 struct snd_soc_component *component = dai->component; in es8328_startup()
461 if (es8328->provider && es8328->sysclk_constraints) in es8328_startup()
462 snd_pcm_hw_constraint_list(substream->runtime, 0, in es8328_startup()
464 es8328->sysclk_constraints); in es8328_startup()
473 struct snd_soc_component *component = dai->component; in es8328_hw_params()
480 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in es8328_hw_params()
485 if (es8328->provider) { in es8328_hw_params()
486 if (!es8328->sysclk_constraints) { in es8328_hw_params()
487 dev_err(component->dev, "No MCLK configured\n"); in es8328_hw_params()
488 return -EINVAL; in es8328_hw_params()
491 for (i = 0; i < es8328->sysclk_constraints->count; i++) in es8328_hw_params()
492 if (es8328->sysclk_constraints->list[i] == in es8328_hw_params()
496 if (i == es8328->sysclk_constraints->count) { in es8328_hw_params()
497 dev_err(component->dev, in es8328_hw_params()
500 return -EINVAL; in es8328_hw_params()
502 ratio = es8328->mclk_ratios[i]; in es8328_hw_params()
505 es8328->mclkdiv2 = 0; in es8328_hw_params()
510 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); in es8328_hw_params()
529 return -EINVAL; in es8328_hw_params()
532 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in es8328_hw_params()
537 es8328->playback_fs = params_rate(params); in es8328_hw_params()
550 struct snd_soc_component *component = codec_dai->component; in es8328_set_sysclk()
556 es8328->sysclk_constraints = NULL; in es8328_set_sysclk()
557 es8328->mclk_ratios = NULL; in es8328_set_sysclk()
563 es8328->sysclk_constraints = &constraints_11289; in es8328_set_sysclk()
564 es8328->mclk_ratios = ratios_11289; in es8328_set_sysclk()
570 es8328->sysclk_constraints = &constraints_12288; in es8328_set_sysclk()
571 es8328->mclk_ratios = ratios_12288; in es8328_set_sysclk()
574 return -EINVAL; in es8328_set_sysclk()
577 es8328->mclkdiv2 = mclkdiv2; in es8328_set_sysclk()
584 struct snd_soc_component *component = codec_dai->component; in es8328_set_dai_fmt()
595 es8328->provider = true; in es8328_set_dai_fmt()
601 es8328->provider = false; in es8328_set_dai_fmt()
604 return -EINVAL; in es8328_set_dai_fmt()
622 return -EINVAL; in es8328_set_dai_fmt()
627 return -EINVAL; in es8328_set_dai_fmt()
698 .name = "es8328-hifi-analog",
724 clk_disable_unprepare(es8328->clk); in es8328_suspend()
726 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_suspend()
727 es8328->supplies); in es8328_suspend()
729 dev_err(component->dev, "unable to disable regulators\n"); in es8328_suspend()
737 struct regmap *regmap = dev_get_regmap(component->dev, NULL); in es8328_resume()
743 ret = clk_prepare_enable(es8328->clk); in es8328_resume()
745 dev_err(component->dev, "unable to enable clock\n"); in es8328_resume()
749 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_resume()
750 es8328->supplies); in es8328_resume()
752 dev_err(component->dev, "unable to enable regulators\n"); in es8328_resume()
759 dev_err(component->dev, "unable to sync regcache\n"); in es8328_resume()
773 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
774 es8328->supplies); in es8328_component_probe()
776 dev_err(component->dev, "unable to enable regulators\n"); in es8328_component_probe()
781 es8328->clk = devm_clk_get(component->dev, NULL); in es8328_component_probe()
782 if (IS_ERR(es8328->clk)) { in es8328_component_probe()
783 dev_err(component->dev, "codec clock missing or invalid\n"); in es8328_component_probe()
784 ret = PTR_ERR(es8328->clk); in es8328_component_probe()
788 ret = clk_prepare_enable(es8328->clk); in es8328_component_probe()
790 dev_err(component->dev, "unable to prepare codec clk\n"); in es8328_component_probe()
797 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
798 es8328->supplies); in es8328_component_probe()
808 clk_disable_unprepare(es8328->clk); in es8328_remove()
810 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_remove()
811 es8328->supplies); in es8328_remove()
853 return -ENOMEM; in es8328_probe()
855 es8328->regmap = regmap; in es8328_probe()
857 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) in es8328_probe()
858 es8328->supplies[i].supply = supply_names[i]; in es8328_probe()
860 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), in es8328_probe()
861 es8328->supplies); in es8328_probe()