soc/codecs/da9055.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
59 /* Input - Gain, Select and Filter Registers */
72 /* Output - Gain, Select and Filter Registers */
250 	/* for MASTER mode, fs = 44.1Khz and its harmonics */
251 	{11289600, 2822400, 0x00, 0x00, 0x20, 1},	/* MCLK=11.2896Mhz */
252 	{12000000, 2822400, 0x03, 0x61, 0x1E, 1},	/* MCLK=12Mhz */
253 	{12288000, 2822400, 0x0C, 0xCC, 0x1D, 1},	/* MCLK=12.288Mhz */
254 	{13000000, 2822400, 0x19, 0x45, 0x1B, 1},	/* MCLK=13Mhz */
255 	{13500000, 2822400, 0x18, 0x56, 0x1A, 1},	/* MCLK=13.5Mhz */
256 	{14400000, 2822400, 0x02, 0xD0, 0x19, 1},	/* MCLK=14.4Mhz */
257 	{19200000, 2822400, 0x1A, 0x1C, 0x12, 1},	/* MCLK=19.2Mhz */
258 	{19680000, 2822400, 0x0B, 0x6D, 0x12, 1},	/* MCLK=19.68Mhz */
259 	{19800000, 2822400, 0x07, 0xDD, 0x12, 1},	/* MCLK=19.8Mhz */
260 	/* for MASTER mode, fs = 48Khz and its harmonics */
261 	{11289600, 3072000, 0x1A, 0x8E, 0x22, 1},	/* MCLK=11.2896Mhz */
262 	{12000000, 3072000, 0x18, 0x93, 0x20, 1},	/* MCLK=12Mhz */
263 	{12288000, 3072000, 0x00, 0x00, 0x20, 1},	/* MCLK=12.288Mhz */
264 	{13000000, 3072000, 0x07, 0xEA, 0x1E, 1},	/* MCLK=13Mhz */
265 	{13500000, 3072000, 0x04, 0x11, 0x1D, 1},	/* MCLK=13.5Mhz */
266 	{14400000, 3072000, 0x09, 0xD0, 0x1B, 1},	/* MCLK=14.4Mhz */
267 	{19200000, 3072000, 0x0F, 0x5C, 0x14, 1},	/* MCLK=19.2Mhz */
268 	{19680000, 3072000, 0x1F, 0x60, 0x13, 1},	/* MCLK=19.68Mhz */
269 	{19800000, 3072000, 0x1B, 0x80, 0x13, 1},	/* MCLK=19.8Mhz */
271 	{11289600, 2822400, 0x0D, 0x47, 0x21, 0},	/* MCLK=11.2896Mhz */
272 	{12000000, 2822400, 0x0D, 0xFA, 0x1F, 0},	/* MCLK=12Mhz */
273 	{12288000, 2822400, 0x16, 0x66, 0x1E, 0},	/* MCLK=12.288Mhz */
274 	{13000000, 2822400, 0x00, 0x98, 0x1D, 0},	/* MCLK=13Mhz */
275 	{13500000, 2822400, 0x1E, 0x33, 0x1B, 0},	/* MCLK=13.5Mhz */
276 	{14400000, 2822400, 0x06, 0x50, 0x1A, 0},	/* MCLK=14.4Mhz */
277 	{19200000, 2822400, 0x14, 0xBC, 0x13, 0},	/* MCLK=19.2Mhz */
278 	{19680000, 2822400, 0x05, 0x66, 0x13, 0},	/* MCLK=19.68Mhz */
279 	{19800000, 2822400, 0x01, 0xAE, 0x13, 0},	/* MCLK=19.8Mhz  */
289 	0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
290 	/* -54dB to 15dB */
291 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
296 	/* -78dB to 12dB */
297 	0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
306 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
307 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
308 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
309 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
310 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
311 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
316 	"Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000"
424 	"44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs",
425 	"5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
433 	"176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs",
434 	"11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs"
442 	"62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs",
443 	"7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs",
444 	"253952/fs", "507904/fs", "1015808/fs", "2031616/fs"
484 	if (ucontrol->value.integer.value[0]) {  in da9055_put_alc_sw()
519 		offset_l = -avg_left_data;  in da9055_put_alc_sw()
520 		offset_r = -avg_right_data;  in da9055_put_alc_sw()
1051 	struct snd_soc_component *component = dai->component;  in da9055_hw_params()
1053 	u8 aif_ctrl, fs;  in da9055_hw_params()  local
1070 		return -EINVAL;  in da9055_hw_params()
1079 		fs		= DA9055_SR_8000;  in da9055_hw_params()
1083 		fs		= DA9055_SR_11025;  in da9055_hw_params()
1087 		fs		= DA9055_SR_12000;  in da9055_hw_params()
1091 		fs		= DA9055_SR_16000;  in da9055_hw_params()
1095 		fs		= DA9055_SR_22050;  in da9055_hw_params()
1099 		fs		= DA9055_SR_32000;  in da9055_hw_params()
1103 		fs		= DA9055_SR_44100;  in da9055_hw_params()
1107 		fs		= DA9055_SR_48000;  in da9055_hw_params()
1111 		fs		= DA9055_SR_88200;  in da9055_hw_params()
1115 		fs		= DA9055_SR_96000;  in da9055_hw_params()
1119 		return -EINVAL;  in da9055_hw_params()
1122 	if (da9055->mclk_rate) {  in da9055_hw_params()
1123 		/* PLL Mode, Write actual FS */  in da9055_hw_params()
1124 		snd_soc_component_write(component, DA9055_SR, fs);  in da9055_hw_params()
1127 		 * Non-PLL Mode  in da9055_hw_params()
1128 		 * When PLL is bypassed, chip assumes constant MCLK of  in da9055_hw_params()
1129 		 * 12.288MHz and uses sample rate value to divide this MCLK  in da9055_hw_params()
1130 		 * to derive its sys clk. As sys clk has to be 256 * Fs, we  in da9055_hw_params()
1136 	if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {  in da9055_hw_params()
1138 		if (!da9055->master) {  in da9055_hw_params()
1159 	struct snd_soc_component *component = codec_dai->component;  in da9055_set_dai_fmt()
1175 		return -EINVAL;  in da9055_set_dai_fmt()
1180 	    (da9055->master != mode))  in da9055_set_dai_fmt()
1181 		return -EINVAL;  in da9055_set_dai_fmt()
1183 	da9055->master = mode;  in da9055_set_dai_fmt()
1200 		return -EINVAL;  in da9055_set_dai_fmt()
1216 	struct snd_soc_component *component = dai->component;  in da9055_mute()
1239 	struct snd_soc_component *component = codec_dai->component;  in da9055_set_dai_sysclk()
1254 			da9055->mclk_rate = freq;  in da9055_set_dai_sysclk()
1257 			dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",  in da9055_set_dai_sysclk()
1259 			return -EINVAL;  in da9055_set_dai_sysclk()
1263 		dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);  in da9055_set_dai_sysclk()
1264 		return -EINVAL;  in da9055_set_dai_sysclk()
1272  * @param fref		: Input MCLK frequency
1282 	struct snd_soc_component *component = codec_dai->component;  in da9055_set_dai_pll()
1291 	if (!da9055->master && (fout != 2822400))  in da9055_set_dai_pll()
1298 		    (da9055->master ==  da9055_pll_div[cnt].mode) &&  in da9055_set_dai_pll()
1317 	dev_err(codec_dai->dev, "Error in setting up PLL\n");  in da9055_set_dai_pll()
1318 	return -EINVAL;  in da9055_set_dai_pll()
1332 	.name = "da9055-hifi",
1426 	if (da9055->pdata) {  in da9055_probe()
1428 		if (da9055->pdata->micbias_source) {  in da9055_probe()
1437 		switch (da9055->pdata->micbias) {  in da9055_probe()
1444 					    (da9055->pdata->micbias) << 4);  in da9055_probe()
1478 	struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);  in da9055_i2c_probe()
1481 	da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),  in da9055_i2c_probe()
1484 		return -ENOMEM;  in da9055_i2c_probe()
1487 		da9055->pdata = pdata;  in da9055_i2c_probe()
1491 	da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);  in da9055_i2c_probe()
1492 	if (IS_ERR(da9055->regmap)) {  in da9055_i2c_probe()
1493 		ret = PTR_ERR(da9055->regmap);  in da9055_i2c_probe()
1494 		dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);  in da9055_i2c_probe()
1498 	ret = devm_snd_soc_register_component(&i2c->dev,  in da9055_i2c_probe()
1501 		dev_err(&i2c->dev, "Failed to register da9055 component: %d\n",  in da9055_i2c_probe()
1515 	{ "da9055-codec", 0 },
1522 	{ .compatible = "dlg,da9055-codec", },
1531 		.name = "da9055-codec",