Lines Matching +full:pdm +full:- +full:fmt
1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and
15 #include <linux/mfd/cs42l43-regs.h>
22 #include <sound/soc-component.h>
23 #include <sound/soc-dapm.h>
24 #include <sound/soc-dai.h>
126 dev_err(priv->dev, "Error " #name " IRQ\n"); \
147 dev_dbg(priv->dev, #name " completed\n"); \
148 complete(&priv->name); \
173 dev_dbg(priv->dev, "Microphone shutter changed\n");
175 if (!priv->component)
179 ret = snd_soc_component_notify_control(priv->component,
193 dev_dbg(priv->dev, "Speaker shutter changed\n");
195 if (!priv->component)
198 ret = snd_soc_component_notify_control(priv->component,
220 struct snd_soc_component *component = dai->component;
222 struct cs42l43 *cs42l43 = priv->core;
223 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap,
228 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
230 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
232 return snd_pcm_hw_constraint_list(substream->runtime, 0,
234 &priv->constraint);
257 return -EINVAL;
265 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
266 struct cs42l43 *cs42l43 = priv->core;
271 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
276 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1,
286 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
287 struct cs42l43 *cs42l43 = priv->core;
288 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
290 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
300 if (priv->n_slots) {
301 n_slots = priv->n_slots;
302 slot_width = priv->slot_width;
306 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
320 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
321 return -EINVAL;
324 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
327 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
331 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
335 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
339 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
341 slots = priv->tx_slots;
344 slots = priv->rx_slots;
356 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
359 regmap_update_bits(cs42l43->regmap, reg,
363 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
371 static int cs42l43_asp_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
373 struct snd_soc_component *component = dai->component;
376 struct cs42l43 *cs42l43 = priv->core;
377 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
387 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
402 dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
403 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
404 return -EINVAL;
407 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
418 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
419 fmt & SND_SOC_DAIFMT_MASTER_MASK);
420 return -EINVAL;
423 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
439 dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
440 fmt & SND_SOC_DAIFMT_INV_MASK);
441 return -EINVAL;
444 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
447 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
451 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
455 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
468 int slot = ffs(mask) - 1;
479 dev_warn(priv->dev, "Too many channels in TDM mask\n");
485 struct snd_soc_component *component = dai->component;
488 priv->n_slots = slots;
489 priv->slot_width = slot_width;
496 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots);
497 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots);
535 .name = "cs42l43-asp",
554 .name = "cs42l43-dp1",
566 .name = "cs42l43-dp2",
578 .name = "cs42l43-dp3",
590 .name = "cs42l43-dp4",
602 .name = "cs42l43-dp5",
614 .name = "cs42l43-dp6",
626 .name = "cs42l43-dp7",
639 static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
655 static const char * const cs42l43_dec_mode_text[] = { "ADC", "PDM" };
674 static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
675 static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
720 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
728 static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
889 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
903 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
912 struct cs42l43 *cs42l43 = priv->core;
914 mutex_lock(&priv->spk_vu_lock);
916 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
918 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
921 mutex_unlock(&priv->spk_vu_lock);
926 struct cs42l43 *cs42l43 = priv->core;
930 ret = pm_runtime_resume_and_get(priv->dev);
932 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
937 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
938 * be cached for the non-volatiles, so drop it from the cache here so
941 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
944 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
948 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
950 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
956 dev_dbg(priv->dev, "%s shutter is %s\n",
961 pm_runtime_mark_last_busy(priv->dev);
962 pm_runtime_put_autosuspend(priv->dev);
978 ucontrol->value.integer.value[0] = ret;
996 ucontrol->value.integer.value[0] = ret;
1149 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1151 struct cs42l43 *cs42l43 = priv->core;
1157 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1161 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1165 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
1166 priv->eq_coeffs[i]);
1168 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1173 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
1177 dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
1179 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1204 struct cs42l43 *cs42l43 = priv->core;
1206 lockdep_assert_held(&cs42l43->pll_lock);
1208 if (priv->refclk_src == src && priv->refclk_freq == freq)
1211 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
1212 dev_err(priv->dev, "PLL active, can't change configuration\n");
1213 return -EBUSY;
1219 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
1222 priv->refclk_src = src;
1223 priv->refclk_freq = freq;
1227 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
1228 return -EINVAL;
1238 struct cs42l43 *cs42l43 = priv->core;
1241 unsigned int freq = priv->refclk_freq;
1244 lockdep_assert_held(&cs42l43->pll_lock);
1246 if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
1248 freq = cs42l43->sdw_freq;
1249 else if (!cs42l43->sdw_freq)
1250 cs42l43->sdw_freq = freq;
1253 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
1255 while (freq > cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq) {
1272 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
1273 return -EINVAL;
1276 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1279 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
1280 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div);
1281 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1284 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
1285 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO,
1286 CS42L43_PLL_CAL_RATIO_MASK, config->cal);
1287 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1290 reinit_completion(&priv->pll_ready);
1292 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1295 time_left = wait_for_completion_timeout(&priv->pll_ready,
1298 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1300 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1303 dev_err(priv->dev, "Timeout out waiting for PLL\n");
1304 return -ETIMEDOUT;
1307 if (priv->refclk_src == CS42L43_SYSCLK_SDW)
1308 cs42l43->sdw_pll_active = true;
1310 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
1317 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq));
1328 struct cs42l43 *cs42l43 = priv->core;
1330 dev_dbg(priv->dev, "Disabling PLL\n");
1332 lockdep_assert_held(&cs42l43->pll_lock);
1334 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq));
1335 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0);
1336 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1339 cs42l43->sdw_pll_active = false;
1347 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1349 struct cs42l43 *cs42l43 = priv->core;
1352 mutex_lock(&cs42l43->pll_lock);
1356 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
1357 ret = clk_prepare_enable(priv->mclk);
1359 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
1369 if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
1370 clk_disable_unprepare(priv->mclk);
1377 mutex_unlock(&cs42l43->pll_lock);
1405 return -ETIMEDOUT;
1413 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1416 return cs42l43_dapm_wait_completion(&priv->spkr_startup,
1417 &priv->spkr_shutdown, event,
1424 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1427 return cs42l43_dapm_wait_completion(&priv->spkl_startup,
1428 &priv->spkl_shutdown, event,
1435 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1437 struct cs42l43 *cs42l43 = priv->core;
1438 unsigned int mask = 1 << w->shift;
1447 priv->hp_ena &= ~mask;
1448 priv->hp_ena |= val;
1450 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1451 &priv->hp_shutdown, event,
1456 if (!priv->load_detect_running)
1457 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
1462 if (priv->load_detect_running)
1465 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1466 &priv->hp_shutdown, event,
1481 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1483 struct cs42l43 *cs42l43 = priv->core;
1488 switch (w->shift) {
1494 val = &priv->decim_cache[0];
1501 val = &priv->decim_cache[1];
1507 val = &priv->decim_cache[2];
1513 val = &priv->decim_cache[3];
1516 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1517 return -EINVAL;
1522 ret = regmap_read(cs42l43->regmap, reg, val);
1524 dev_err(priv->dev,
1530 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute);
1533 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val);
1545 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1547 struct cs42l43 *cs42l43 = priv->core;
1548 unsigned int mask = 1 << w->shift;
1561 priv->adc_ena &= ~mask;
1562 priv->adc_ena |= val;
1564 if (!priv->load_detect_running)
1565 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
1673 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
1850 { "Decimator 1 Mode", "PDM", "PDM1L" },
1852 { "Decimator 2 Mode", "PDM", "PDM1R" },
1909 { "AMP1", NULL, "vdd-amp" },
1910 { "AMP2", NULL, "vdd-amp" },
2001 struct cs42l43 *cs42l43 = priv->core;
2004 mutex_lock(&cs42l43->pll_lock);
2006 mutex_unlock(&cs42l43->pll_lock);
2014 struct cs42l43 *cs42l43 = priv->core;
2016 snd_soc_component_init_regmap(component, cs42l43->regmap);
2018 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots);
2019 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots);
2021 priv->component = component;
2022 priv->constraint = cs42l43_constraint;
2028 .name = "cs42l43-codec",
2088 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name);
2090 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
2092 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler,
2095 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name);
2111 dev_warn(priv->dev, "Manual shutters, notifications not available\n");
2138 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
2144 dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY);
2146 return -EPROBE_DEFER;
2148 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2150 return -ENOMEM;
2152 priv->dev = &pdev->dev;
2153 priv->core = cs42l43;
2157 mutex_init(&priv->jack_lock);
2158 mutex_init(&priv->spk_vu_lock);
2160 init_completion(&priv->hp_startup);
2161 init_completion(&priv->hp_shutdown);
2162 init_completion(&priv->spkr_shutdown);
2163 init_completion(&priv->spkl_shutdown);
2164 init_completion(&priv->spkr_startup);
2165 init_completion(&priv->spkl_startup);
2166 init_completion(&priv->pll_ready);
2167 init_completion(&priv->type_detect);
2168 init_completion(&priv->load_detect);
2170 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
2171 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
2172 INIT_DELAYED_WORK(&priv->button_press_work, cs42l43_button_press_work);
2173 INIT_WORK(&priv->button_release_work, cs42l43_button_release_work);
2175 pm_runtime_set_autosuspend_delay(priv->dev, 100);
2176 pm_runtime_use_autosuspend(priv->dev);
2177 pm_runtime_set_active(priv->dev);
2178 pm_runtime_get_noresume(priv->dev);
2180 ret = devm_pm_runtime_enable(priv->dev);
2192 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
2194 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
2212 priv->mclk = clk_get_optional(cs42l43->dev, "mclk");
2213 if (IS_ERR(priv->mclk)) {
2214 ret = PTR_ERR(priv->mclk);
2215 dev_err_probe(priv->dev, ret, "Failed to get mclk\n");
2219 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv,
2222 dev_err_probe(priv->dev, ret, "Failed to register component\n");
2226 pm_runtime_mark_last_busy(priv->dev);
2227 pm_runtime_put_autosuspend(priv->dev);
2232 clk_put(priv->mclk);
2234 pm_runtime_put_sync(priv->dev);
2243 clk_put(priv->mclk);
2252 dev_dbg(priv->dev, "Runtime resume\n");
2264 { "cs42l43-codec", },
2271 .name = "cs42l43-codec",