Lines Matching +full:0 +full:x00000033
20 { CS35L41_PWR_CTRL1, 0x00000000 },
21 { CS35L41_PWR_CTRL2, 0x00000000 },
22 { CS35L41_PWR_CTRL3, 0x01000010 },
23 { CS35L41_GPIO_PAD_CONTROL, 0x00000000 },
24 { CS35L41_GLOBAL_CLK_CTRL, 0x00000003 },
25 { CS35L41_TST_FS_MON0, 0x00020016 },
26 { CS35L41_BSTCVRT_COEFF, 0x00002424 },
27 { CS35L41_BSTCVRT_SLOPE_LBST, 0x00007500 },
28 { CS35L41_BSTCVRT_PEAK_CUR, 0x0000004A },
29 { CS35L41_SP_ENABLES, 0x00000000 },
30 { CS35L41_SP_RATE_CTRL, 0x00000028 },
31 { CS35L41_SP_FORMAT, 0x18180200 },
32 { CS35L41_SP_HIZ_CTRL, 0x00000002 },
33 { CS35L41_SP_FRAME_TX_SLOT, 0x03020100 },
34 { CS35L41_SP_FRAME_RX_SLOT, 0x00000100 },
35 { CS35L41_SP_TX_WL, 0x00000018 },
36 { CS35L41_SP_RX_WL, 0x00000018 },
37 { CS35L41_DAC_PCM1_SRC, 0x00000008 },
38 { CS35L41_ASP_TX1_SRC, 0x00000018 },
39 { CS35L41_ASP_TX2_SRC, 0x00000019 },
40 { CS35L41_ASP_TX3_SRC, 0x00000000 },
41 { CS35L41_ASP_TX4_SRC, 0x00000000 },
42 { CS35L41_DSP1_RX1_SRC, 0x00000008 },
43 { CS35L41_DSP1_RX2_SRC, 0x00000009 },
44 { CS35L41_DSP1_RX3_SRC, 0x00000018 },
45 { CS35L41_DSP1_RX4_SRC, 0x00000019 },
46 { CS35L41_DSP1_RX5_SRC, 0x00000020 },
47 { CS35L41_DSP1_RX6_SRC, 0x00000021 },
48 { CS35L41_DSP1_RX7_SRC, 0x0000003A },
49 { CS35L41_DSP1_RX8_SRC, 0x0000003B },
50 { CS35L41_NGATE1_SRC, 0x00000008 },
51 { CS35L41_NGATE2_SRC, 0x00000009 },
52 { CS35L41_AMP_DIG_VOL_CTRL, 0x00008000 },
53 { CS35L41_CLASSH_CFG, 0x000B0405 },
54 { CS35L41_WKFET_CFG, 0x00000111 },
55 { CS35L41_NG_CFG, 0x00000033 },
56 { CS35L41_AMP_GAIN_CTRL, 0x00000000 },
57 { CS35L41_IRQ1_MASK1, 0xFFFFFFFF },
58 { CS35L41_IRQ1_MASK2, 0xFFFFFFFF },
59 { CS35L41_IRQ1_MASK3, 0xFFFF87FF },
60 { CS35L41_IRQ1_MASK4, 0xFEFFFFFF },
61 { CS35L41_GPIO1_CTRL1, 0x81000001 },
62 { CS35L41_GPIO2_CTRL1, 0x81000001 },
63 { CS35L41_MIXER_NGATE_CFG, 0x00000000 },
64 { CS35L41_MIXER_NGATE_CH1_CFG, 0x00000303 },
65 { CS35L41_MIXER_NGATE_CH2_CFG, 0x00000303 },
66 { CS35L41_DSP1_CCM_CORE_CTRL, 0x00000101 },
428 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
429 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
430 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
431 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
432 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
433 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
434 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
435 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
436 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
437 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
438 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
439 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
440 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
441 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
442 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
443 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
444 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
445 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
446 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
447 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
448 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
449 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
450 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
451 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
452 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
453 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
454 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
455 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
456 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
457 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
458 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
459 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
460 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
461 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
462 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
463 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
464 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
465 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
466 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
467 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
468 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
469 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
470 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
471 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
472 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
473 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
474 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
475 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
476 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
477 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
478 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
479 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
480 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
481 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
482 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
483 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
484 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
485 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
486 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
487 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
488 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
489 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
490 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
491 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
492 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
493 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
494 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
495 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
496 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
497 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
498 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
499 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
500 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
501 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
502 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
503 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
504 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
505 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
506 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
507 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
508 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
509 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
510 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
511 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/
512 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
513 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
514 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
515 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
516 { 0x00007434, 17, 1 }, /*FORCE_CAL*/
517 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
518 { 0x00007068, 0, 9 }, /*MODIX*/
519 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
520 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/
521 { 0x00000000, 0, 1 }, /*extra bit*/
522 { 0x00017040, 0, 8 }, /*X_COORDINATE*/
523 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
524 { 0x00017040, 16, 8 }, /*WAFER_ID*/
525 { 0x00017040, 24, 8 }, /*DVS*/
526 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/
531 { 0x00002030, 0, 4 }, /*TRIM_OSC_FREQ_TRIM*/
532 { 0x00002030, 7, 1 }, /*TRIM_OSC_TRIM_DONE*/
533 { 0x0000208c, 24, 6 }, /*TST_DIGREG_VREF_TRIM*/
534 { 0x00002090, 14, 4 }, /*TST_REF_TRIM*/
535 { 0x00002090, 10, 4 }, /*TST_REF_TEMPCO_TRIM*/
536 { 0x0000300C, 11, 4 }, /*PLL_LDOA_TST_VREF_TRIM*/
537 { 0x0000394C, 23, 2 }, /*BST_ATEST_CM_VOFF*/
538 { 0x00003950, 0, 7 }, /*BST_ATRIM_IADC_OFFSET*/
539 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
540 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
541 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
542 { 0x00003954, 0, 7 }, /*BST_ATRIM_IADC_OFFSET2*/
543 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
544 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
545 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
546 { 0x00003958, 0, 7 }, /*BST_ATRIM_IADC_OFFSET3*/
547 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
548 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
549 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
550 { 0x0000395C, 0, 7 }, /*BST_ATRIM_IADC_OFFSET4*/
551 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
552 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
553 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
554 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
555 { 0x00004160, 0, 7 }, /*VMON_OFFSET_OTP_VAL*/
556 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
557 { 0x00004160, 16, 10 }, /*IMON_OFFSET_OTP_VAL*/
558 { 0x0000416C, 16, 12 }, /*VMON_CM_GAIN_OTP_VAL*/
559 { 0x0000416C, 28, 1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
560 { 0x00004170, 0, 6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
561 { 0x00004170, 6, 1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
562 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
563 { 0x00004170, 14, 1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
564 { 0x00004170, 16, 9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
565 { 0x00004360, 0, 5 }, /*TEMP_GAIN_OTP_VAL*/
566 { 0x00004360, 6, 9 }, /*TEMP_OFFSET_OTP_VAL*/
567 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
568 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
569 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
570 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
571 { 0x0000444C, 0, 3 }, /*ANA_SELINVREF*/
572 { 0x00006E30, 0, 5 }, /*GAIN_ERR_COEFF_0*/
573 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
574 { 0x00006E30, 16, 5 }, /*GAIN_ERR_COEFF_2*/
575 { 0x00006E30, 24, 5 }, /*GAIN_ERR_COEFF_3*/
576 { 0x00006E34, 0, 5 }, /*GAIN_ERR_COEFF_4*/
577 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
578 { 0x00006E34, 16, 5 }, /*GAIN_ERR_COEFF_6*/
579 { 0x00006E34, 24, 5 }, /*GAIN_ERR_COEFF_7*/
580 { 0x00006E38, 0, 5 }, /*GAIN_ERR_COEFF_8*/
581 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
582 { 0x00006E38, 16, 5 }, /*GAIN_ERR_COEFF_10*/
583 { 0x00006E38, 24, 5 }, /*GAIN_ERR_COEFF_11*/
584 { 0x00006E3C, 0, 5 }, /*GAIN_ERR_COEFF_12*/
585 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
586 { 0x00006E3C, 16, 5 }, /*GAIN_ERR_COEFF_14*/
587 { 0x00006E3C, 24, 5 }, /*GAIN_ERR_COEFF_15*/
588 { 0x00006E40, 0, 5 }, /*GAIN_ERR_COEFF_16*/
589 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
590 { 0x00006E40, 16, 5 }, /*GAIN_ERR_COEFF_18*/
591 { 0x00006E40, 24, 5 }, /*GAIN_ERR_COEFF_19*/
592 { 0x00006E44, 0, 5 }, /*GAIN_ERR_COEFF_20*/
593 { 0x00006E48, 0, 10 }, /*VOFF_GAIN_0*/
594 { 0x00006E48, 10, 10 }, /*VOFF_GAIN_1*/
595 { 0x00006E48, 20, 10 }, /*VOFF_GAIN_2*/
596 { 0x00006E4C, 0, 10 }, /*VOFF_GAIN_3*/
597 { 0x00006E4C, 10, 10 }, /*VOFF_GAIN_4*/
598 { 0x00006E4C, 20, 10 }, /*VOFF_GAIN_5*/
599 { 0x00006E50, 0, 10 }, /*VOFF_GAIN_6*/
600 { 0x00006E50, 10, 10 }, /*VOFF_GAIN_7*/
601 { 0x00006E50, 20, 10 }, /*VOFF_GAIN_8*/
602 { 0x00006E54, 0, 10 }, /*VOFF_GAIN_9*/
603 { 0x00006E54, 10, 10 }, /*VOFF_GAIN_10*/
604 { 0x00006E54, 20, 10 }, /*VOFF_GAIN_11*/
605 { 0x00006E58, 0, 10 }, /*VOFF_GAIN_12*/
606 { 0x00006E58, 10, 10 }, /*VOFF_GAIN_13*/
607 { 0x00006E58, 20, 10 }, /*VOFF_GAIN_14*/
608 { 0x00006E5C, 0, 10 }, /*VOFF_GAIN_15*/
609 { 0x00006E5C, 10, 10 }, /*VOFF_GAIN_16*/
610 { 0x00006E5C, 20, 10 }, /*VOFF_GAIN_17*/
611 { 0x00006E60, 0, 10 }, /*VOFF_GAIN_18*/
612 { 0x00006E60, 10, 10 }, /*VOFF_GAIN_19*/
613 { 0x00006E60, 20, 10 }, /*VOFF_GAIN_20*/
614 { 0x00006E64, 0, 10 }, /*VOFF_INT1*/
615 { 0x00007418, 7, 5 }, /*DS_SPK_INT1_CAP_TRIM*/
616 { 0x0000741C, 0, 5 }, /*DS_SPK_INT2_CAP_TRIM*/
617 { 0x0000741C, 11, 4 }, /*DS_SPK_LPF_CAP_TRIM*/
618 { 0x0000741C, 19, 4 }, /*DS_SPK_QUAN_CAP_TRIM*/
619 { 0x00007434, 17, 1 }, /*FORCE_CAL*/
620 { 0x00007434, 18, 7 }, /*CAL_OVERRIDE*/
621 { 0x00007068, 0, 9 }, /*MODIX*/
622 { 0x0000410C, 7, 1 }, /*VIMON_DLY_NOT_COMB*/
623 { 0x0000400C, 0, 7 }, /*VIMON_DLY*/
624 { 0x00004000, 11, 1 }, /*VMON_POL*/
625 { 0x00017040, 0, 8 }, /*X_COORDINATE*/
626 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
627 { 0x00017040, 16, 8 }, /*WAFER_ID*/
628 { 0x00017040, 24, 8 }, /*DVS*/
629 { 0x00017044, 0, 24 }, /*LOT_NUMBER*/
633 { 0x00003854, 0x05180240 },
634 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
635 { 0x00004310, 0x00000000 },
636 { CS35L41_VPVBST_FS_SEL, 0x00000000 },
637 { CS35L41_OTP_TRIM_30, 0x9091A1C8 },
638 { 0x00003014, 0x0200EE0E },
639 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
640 { 0x00000054, 0x00000004 },
641 { CS35L41_IRQ1_DB3, 0x00000000 },
642 { CS35L41_IRQ2_DB3, 0x00000000 },
643 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
644 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
645 { CS35L41_PWR_CTRL2, 0x00000000 },
646 { CS35L41_AMP_GAIN_CTRL, 0x00000000 },
647 { CS35L41_ASP_TX3_SRC, 0x00000000 },
648 { CS35L41_ASP_TX4_SRC, 0x00000000 },
652 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
653 { 0x00004310, 0x00000000 },
654 { CS35L41_VPVBST_FS_SEL, 0x00000000 },
655 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
656 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
657 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
658 { CS35L41_PWR_CTRL2, 0x00000000 },
659 { CS35L41_AMP_GAIN_CTRL, 0x00000000 },
660 { CS35L41_ASP_TX3_SRC, 0x00000000 },
661 { CS35L41_ASP_TX4_SRC, 0x00000000 },
665 { CS35L41_VIMON_SPKMON_RESYNC, 0x00000000 },
666 { 0x00004310, 0x00000000 },
667 { CS35L41_VPVBST_FS_SEL, 0x00000000 },
668 { CS35L41_BSTCVRT_DCM_CTRL, 0x00000051 },
669 { CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
670 { CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
671 { CS35L41_PWR_CTRL2, 0x00000000 },
672 { CS35L41_AMP_GAIN_CTRL, 0x00000000 },
673 { CS35L41_ASP_TX3_SRC, 0x00000000 },
674 { CS35L41_ASP_TX4_SRC, 0x00000000 },
678 { CS35L41_DSP1_RX1_RATE, 0x00000001 },
679 { CS35L41_DSP1_RX2_RATE, 0x00000001 },
680 { CS35L41_DSP1_RX3_RATE, 0x00000001 },
681 { CS35L41_DSP1_RX4_RATE, 0x00000001 },
682 { CS35L41_DSP1_RX5_RATE, 0x00000001 },
683 { CS35L41_DSP1_RX6_RATE, 0x00000001 },
684 { CS35L41_DSP1_RX7_RATE, 0x00000001 },
685 { CS35L41_DSP1_RX8_RATE, 0x00000001 },
686 { CS35L41_DSP1_TX1_RATE, 0x00000001 },
687 { CS35L41_DSP1_TX2_RATE, 0x00000001 },
688 { CS35L41_DSP1_TX3_RATE, 0x00000001 },
689 { CS35L41_DSP1_TX4_RATE, 0x00000001 },
690 { CS35L41_DSP1_TX5_RATE, 0x00000001 },
691 { CS35L41_DSP1_TX6_RATE, 0x00000001 },
692 { CS35L41_DSP1_TX7_RATE, 0x00000001 },
693 { CS35L41_DSP1_TX8_RATE, 0x00000001 },
698 .id = 0x01,
705 .id = 0x02,
712 .id = 0x03,
719 .id = 0x06,
726 .id = 0x08,
771 for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) { in cs35l41_find_otp_map()
782 { CS35L41_TEST_KEY_CTL, 0x00000055 }, in cs35l41_test_key_unlock()
783 { CS35L41_TEST_KEY_CTL, 0x000000AA }, in cs35l41_test_key_unlock()
798 { CS35L41_TEST_KEY_CTL, 0x000000CC }, in cs35l41_test_key_lock()
799 { CS35L41_TEST_KEY_CTL, 0x00000033 }, in cs35l41_test_key_lock()
850 for (i = 0; i < otp_map_match->num_elements; i++) { in cs35l41_otp_unpack()
857 GENMASK(bit_offset + otp_map[i].size - 33, 0)) << in cs35l41_otp_unpack()
860 } else if (bit_offset + otp_map[i].size - 1 >= 0) { in cs35l41_otp_unpack()
865 } else /* both bit_offset and otp_map[i].size are 0 */ in cs35l41_otp_unpack()
866 otp_val = 0; in cs35l41_otp_unpack()
871 bit_offset = 0; in cs35l41_otp_unpack()
875 if (otp_map[i].reg != 0) { in cs35l41_otp_unpack()
880 if (ret < 0) { in cs35l41_otp_unpack()
887 ret = 0; in cs35l41_otp_unpack()
927 ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0); in cs35l41_register_errata_patch()
928 if (ret < 0) in cs35l41_register_errata_patch()
945 val = 0; in cs35l41_set_channels()
946 mask = 0; in cs35l41_set_channels()
947 for (i = 0; i < rx_num; i++) { in cs35l41_set_channels()
950 mask |= 0x3F << (i * 8); in cs35l41_set_channels()
954 val = 0; in cs35l41_set_channels()
955 mask = 0; in cs35l41_set_channels()
956 for (i = 0; i < tx_num; i++) { in cs35l41_set_channels()
959 mask |= 0x3F << (i * 8); in cs35l41_set_channels()
963 return 0; in cs35l41_set_channels()
968 { 0x24, 0x32, 0x32, 0x4F, 0x57 },
969 { 0x24, 0x32, 0x32, 0x4F, 0x57 },
970 { 0x40, 0x32, 0x32, 0x4F, 0x57 },
971 { 0x40, 0x32, 0x32, 0x4F, 0x57 }
975 { 0x24, 0x49, 0x66, 0xA3, 0xEA },
976 { 0x24, 0x49, 0x66, 0xA3, 0xEA },
977 { 0x48, 0x49, 0x66, 0xA3, 0xEA },
978 { 0x48, 0x49, 0x66, 0xA3, 0xEA }
982 0x75, 0x6B, 0x3B, 0x28
993 bst_lbst_val = 0; in cs35l41_boost_config()
1010 case 0 ... 19: in cs35l41_boost_config()
1011 bst_cbst_range = 0; in cs35l41_boost_config()
1023 if (boost_cap < 0) { in cs35l41_boost_config()
1057 bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10; in cs35l41_boost_config()
1069 return 0; in cs35l41_boost_config()
1073 { 0x00000040, 0x00000055 },
1074 { 0x00000040, 0x000000AA },
1075 { 0x0000393C, 0x000000C0, 6000},
1076 { 0x0000393C, 0x00000000 },
1077 { 0x00007414, 0x00C82222 },
1078 { 0x0000742C, 0x00000000 },
1079 { 0x00000040, 0x000000CC },
1080 { 0x00000040, 0x00000033 },
1084 { 0x00000040, 0x00000055 },
1085 { 0x00000040, 0x000000AA },
1086 { 0x00007438, 0x00585941 },
1087 { CS35L41_PWR_CTRL1, 0x00000000 },
1088 { 0x0000742C, 0x00000009 },
1092 { 0x00007438, 0x00580941 },
1093 { 0x00000040, 0x000000CC },
1094 { 0x00000040, 0x00000033 },
1098 { 0x00000040, 0x00000055 },
1099 { 0x00000040, 0x000000AA },
1100 { 0x0000742C, 0x0000000F },
1101 { 0x0000742C, 0x00000079 },
1102 { 0x00007438, 0x00585941 },
1103 { CS35L41_PWR_CTRL1, 0x00000001 }, // GLOBAL_EN = 1
1107 { 0x0000742C, 0x000000F9 },
1108 { 0x00007438, 0x00580941 },
1112 { 0x00000040, 0x00000055 },
1113 { 0x00000040, 0x000000AA },
1114 { 0x00007438, 0x00585941 },
1115 { 0x00007414, 0x08C82222 },
1116 { 0x0000742C, 0x00000009 },
1117 { 0x00000040, 0x000000CC },
1118 { 0x00000040, 0x00000033 },
1123 {CS35L41_MDSYNC_EN, 0x00003000},
1125 {CS35L41_BSTCVRT_VCTRL2, 0x00000002},
1129 /* SYNC_BST_CTL_RX_EN = 0; SYNC_BST_CTL_TX_EN = 1 */
1130 {CS35L41_MDSYNC_EN, 0x00001000},
1131 /* BST_EN = 0 */
1132 {CS35L41_PWR_CTRL2, 0x00003300},
1134 {CS35L41_BSTCVRT_VCTRL2, 0x00000002},
1158 regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); in cs35l41_init_boost()
1185 regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001); in cs35l41_safe_reset()
1222 {CS35L41_PWR_CTRL3, 0}, in cs35l41_global_enable()
1223 {CS35L41_GPIO_PAD_CONTROL, 0}, in cs35l41_global_enable()
1224 {CS35L41_PWR_CTRL1, 0, 3000}, in cs35l41_global_enable()
1235 return 0; in cs35l41_global_enable()
1238 return 0; in cs35l41_global_enable()
1256 cs35l41_mdsync_down_seq[0].def = pwr_ctrl3; in cs35l41_global_enable()
1418 dsp->rev = 0; in cs35l41_configure_cs_dsp()
1425 dsp->lock_regions = 0xFFFFFFFF; in cs35l41_configure_cs_dsp()
1455 unsigned int sts = 0, i; in cs35l41_set_cspl_mbox_cmd()
1460 if (ret < 0) { in cs35l41_set_cspl_mbox_cmd()
1467 for (i = 0; i < 5; i++) { in cs35l41_set_cspl_mbox_cmd()
1471 if (ret < 0) { in cs35l41_set_cspl_mbox_cmd()
1479 return 0; in cs35l41_set_cspl_mbox_cmd()
1495 if (ret < 0) in cs35l41_write_fs_errata()
1511 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088); in cs35l41_enter_hibernate()
1512 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188); in cs35l41_enter_hibernate()
1517 return 0; in cs35l41_enter_hibernate()
1527 for (i = 0; i < pwrmgt_retries; i++) { in cs35l41_wait_for_pwrmgt_sts()
1546 for (i = 0; i < sleep_retries; i++) { in cs35l41_exit_hibernate()
1549 for (j = 0; j < wake_retries; j++) { in cs35l41_exit_hibernate()
1560 return 0; in cs35l41_exit_hibernate()
1566 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088); in cs35l41_exit_hibernate()
1569 regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188); in cs35l41_exit_hibernate()
1572 regmap_write(regmap, CS35L41_PWRMGT_CTL, 0x3); in cs35l41_exit_hibernate()