Lines Matching refs:ADAU1373_DRC
106 #define ADAU1373_DRC(x) (0x80 + (x) * 0x10) macro
264 { ADAU1373_DRC(0) + 0x0, 0x78 },
265 { ADAU1373_DRC(0) + 0x1, 0x18 },
266 { ADAU1373_DRC(0) + 0x2, 0x00 },
267 { ADAU1373_DRC(0) + 0x3, 0x00 },
268 { ADAU1373_DRC(0) + 0x4, 0x00 },
269 { ADAU1373_DRC(0) + 0x5, 0xc0 },
270 { ADAU1373_DRC(0) + 0x6, 0x00 },
271 { ADAU1373_DRC(0) + 0x7, 0x00 },
272 { ADAU1373_DRC(0) + 0x8, 0x00 },
273 { ADAU1373_DRC(0) + 0x9, 0xc0 },
274 { ADAU1373_DRC(0) + 0xa, 0x88 },
275 { ADAU1373_DRC(0) + 0xb, 0x7a },
276 { ADAU1373_DRC(0) + 0xc, 0xdf },
277 { ADAU1373_DRC(0) + 0xd, 0x20 },
278 { ADAU1373_DRC(0) + 0xe, 0x00 },
279 { ADAU1373_DRC(0) + 0xf, 0x00 },
280 { ADAU1373_DRC(1) + 0x0, 0x78 },
281 { ADAU1373_DRC(1) + 0x1, 0x18 },
282 { ADAU1373_DRC(1) + 0x2, 0x00 },
283 { ADAU1373_DRC(1) + 0x3, 0x00 },
284 { ADAU1373_DRC(1) + 0x4, 0x00 },
285 { ADAU1373_DRC(1) + 0x5, 0xc0 },
286 { ADAU1373_DRC(1) + 0x6, 0x00 },
287 { ADAU1373_DRC(1) + 0x7, 0x00 },
288 { ADAU1373_DRC(1) + 0x8, 0x00 },
289 { ADAU1373_DRC(1) + 0x9, 0xc0 },
290 { ADAU1373_DRC(1) + 0xa, 0x88 },
291 { ADAU1373_DRC(1) + 0xb, 0x7a },
292 { ADAU1373_DRC(1) + 0xc, 0xdf },
293 { ADAU1373_DRC(1) + 0xd, 0x20 },
294 { ADAU1373_DRC(1) + 0xe, 0x00 },
295 { ADAU1373_DRC(1) + 0xf, 0x00 },
296 { ADAU1373_DRC(2) + 0x0, 0x78 },
297 { ADAU1373_DRC(2) + 0x1, 0x18 },
298 { ADAU1373_DRC(2) + 0x2, 0x00 },
299 { ADAU1373_DRC(2) + 0x3, 0x00 },
300 { ADAU1373_DRC(2) + 0x4, 0x00 },
301 { ADAU1373_DRC(2) + 0x5, 0xc0 },
302 { ADAU1373_DRC(2) + 0x6, 0x00 },
303 { ADAU1373_DRC(2) + 0x7, 0x00 },
304 { ADAU1373_DRC(2) + 0x8, 0x00 },
305 { ADAU1373_DRC(2) + 0x9, 0xc0 },
306 { ADAU1373_DRC(2) + 0xa, 0x88 },
307 { ADAU1373_DRC(2) + 0xb, 0x7a },
308 { ADAU1373_DRC(2) + 0xc, 0xdf },
309 { ADAU1373_DRC(2) + 0xd, 0x20 },
310 { ADAU1373_DRC(2) + 0xe, 0x00 },
311 { ADAU1373_DRC(2) + 0xf, 0x00 },
1332 regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]); in adau1373_load_drc_settings()