118 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg)  in acp_reg_read()  argument
120 	return readl(acp_mmio + (reg * 4));  in acp_reg_read()
123 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg)  in acp_reg_write()  argument
125 	writel(val, acp_mmio + (reg * 4));  in acp_reg_write()
132 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num,  in config_acp_dma_channel()  argument
139 	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in config_acp_dma_channel()
141 	acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in config_acp_dma_channel()
146 			acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num);  in config_acp_dma_channel()
153 		      acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num);  in config_acp_dma_channel()
156 	acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num);  in config_acp_dma_channel()
160 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio,  in config_dma_descriptor_in_sram()  argument
169 	acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr);  in config_dma_descriptor_in_sram()
170 	acp_reg_write(descr_info->src,	acp_mmio, mmACP_SRBM_Targ_Idx_Data);  in config_dma_descriptor_in_sram()
172 	acp_reg_write(sram_offset + 4,	acp_mmio, mmACP_SRBM_Targ_Idx_Addr);  in config_dma_descriptor_in_sram()
173 	acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data);  in config_dma_descriptor_in_sram()
176 	acp_reg_write(sram_offset + 8,	acp_mmio, mmACP_SRBM_Targ_Idx_Addr);  in config_dma_descriptor_in_sram()
177 	acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data);  in config_dma_descriptor_in_sram()
180 static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num)  in pre_config_reset()  argument
186 	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in pre_config_reset()
188 	acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in pre_config_reset()
190 	ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4),  in pre_config_reset()
202 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio,  in set_acp_sysmem_dma_descriptors()  argument
247 		config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,  in set_acp_sysmem_dma_descriptors()
250 	pre_config_reset(acp_mmio, ch);  in set_acp_sysmem_dma_descriptors()
251 	config_acp_dma_channel(acp_mmio, ch,  in set_acp_sysmem_dma_descriptors()
261 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size,  in set_acp_to_i2s_dma_descriptors()  argument
287 		config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx,  in set_acp_to_i2s_dma_descriptors()
290 	pre_config_reset(acp_mmio, ch);  in set_acp_to_i2s_dma_descriptors()
292 	config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1,  in set_acp_to_i2s_dma_descriptors()
298 static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr,  in acp_pte_config()  argument
310 			      acp_mmio, mmACP_SRBM_Targ_Idx_Addr);  in acp_pte_config()
315 		acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data);  in acp_pte_config()
319 			      acp_mmio, mmACP_SRBM_Targ_Idx_Addr);  in acp_pte_config()
323 		acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data);  in acp_pte_config()
330 static void config_acp_dma(void __iomem *acp_mmio,  in config_acp_dma()  argument
336 	acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages,  in config_acp_dma()
347 	set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,  in config_acp_dma()
352 	set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,  in config_acp_dma()
358 static void acp_dma_cap_channel_enable(void __iomem *acp_mmio,  in acp_dma_cap_channel_enable()  argument
376 	val = acp_reg_read(acp_mmio,  in acp_dma_cap_channel_enable()
379 		acp_reg_write(0x0, acp_mmio, ch_reg);  in acp_dma_cap_channel_enable()
381 		acp_reg_write(0x2, acp_mmio, res_reg);  in acp_dma_cap_channel_enable()
383 	val = acp_reg_read(acp_mmio, imr_reg);  in acp_dma_cap_channel_enable()
386 	acp_reg_write(val, acp_mmio, imr_reg);  in acp_dma_cap_channel_enable()
387 	acp_reg_write(0x1, acp_mmio, ch_reg);  in acp_dma_cap_channel_enable()
390 static void acp_dma_cap_channel_disable(void __iomem *acp_mmio,  in acp_dma_cap_channel_disable()  argument
406 	val = acp_reg_read(acp_mmio, imr_reg);  in acp_dma_cap_channel_disable()
409 	acp_reg_write(val, acp_mmio, imr_reg);  in acp_dma_cap_channel_disable()
410 	acp_reg_write(0x0, acp_mmio, ch_reg);  in acp_dma_cap_channel_disable()
414 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular)  in acp_dma_start()  argument
419 	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in acp_dma_start()
422 	acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL);  in acp_dma_start()
450 	acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in acp_dma_start()
454 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num)  in acp_dma_stop()  argument
460 	dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in acp_dma_stop()
469 	acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in acp_dma_stop()
470 	dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);  in acp_dma_stop()
478 		acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num);  in acp_dma_stop()
483 		dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS);  in acp_dma_stop()
491 			acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0  in acp_dma_stop()
504 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank,  in acp_set_sram_bank_state()  argument
522 	val = acp_reg_read(acp_mmio, req_reg);  in acp_set_sram_bank_state()
540 	acp_reg_write(val, acp_mmio, req_reg);  in acp_set_sram_bank_state()
542 	while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) {  in acp_set_sram_bank_state()
552 static int acp_init(void __iomem *acp_mmio, u32 asic_type)  in acp_init()  argument
558 	val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);  in acp_init()
561 	acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);  in acp_init()
565 		val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);  in acp_init()
577 	val = acp_reg_read(acp_mmio, mmACP_CONTROL);  in acp_init()
579 	acp_reg_write(val, acp_mmio, mmACP_CONTROL);  in acp_init()
584 		val = acp_reg_read(acp_mmio, mmACP_STATUS);  in acp_init()
595 	val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);  in acp_init()
597 	acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);  in acp_init()
601 		val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL);  in acp_init()
603 		acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL);  in acp_init()
607 	acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio,  in acp_init()
611 	acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio,  in acp_init()
618 	acp_reg_write(sram_pte_offset,  acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1);  in acp_init()
619 	acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio,  in acp_init()
622 	acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio,  in acp_init()
626 	acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR);  in acp_init()
628 		      acp_mmio, mmACP_EXTERNAL_INTR_CNTL);  in acp_init()
640 			acp_set_sram_bank_state(acp_mmio, bank, false);  in acp_init()
646 static int acp_deinit(void __iomem *acp_mmio)  in acp_deinit()  argument
652 	val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);  in acp_deinit()
655 	acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET);  in acp_deinit()
659 		val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET);  in acp_deinit()
670 	val = acp_reg_read(acp_mmio, mmACP_CONTROL);  in acp_deinit()
672 	acp_reg_write(val, acp_mmio, mmACP_CONTROL);  in acp_deinit()
677 		val = acp_reg_read(acp_mmio, mmACP_STATUS);  in acp_deinit()
695 	void __iomem *acp_mmio;  in dma_irq_handler()  local
700 	acp_mmio = irq_data->acp_mmio;  in dma_irq_handler()
702 	ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT);  in dma_irq_handler()
711 			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);  in dma_irq_handler()
718 			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);  in dma_irq_handler()
726 			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);  in dma_irq_handler()
731 		if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) ==  in dma_irq_handler()
736 		config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx,  in dma_irq_handler()
738 		acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false);  in dma_irq_handler()
742 			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);  in dma_irq_handler()
747 		if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) ==  in dma_irq_handler()
752 		config_acp_dma_channel(acp_mmio,  in dma_irq_handler()
755 		acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM,  in dma_irq_handler()
761 			      acp_mmio, mmACP_EXTERNAL_INTR_STAT);  in dma_irq_handler()
808 	adata->acp_mmio = intr_data->acp_mmio;  in acp_dma_open()
820 		acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);  in acp_dma_open()
830 				acp_set_sram_bank_state(intr_data->acp_mmio,  in acp_dma_open()
836 				acp_set_sram_bank_state(intr_data->acp_mmio,  in acp_dma_open()
872 		val = acp_reg_read(adata->acp_mmio,  in acp_dma_hw_params()
897 		acp_reg_write(val, adata->acp_mmio,  in acp_dma_hw_params()
1005 	acp_set_sram_bank_state(rtd->acp_mmio, 0, true);  in acp_dma_hw_params()
1015 	config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type);  in acp_dma_hw_params()
1023 	byte_count.bcount.high = acp_reg_read(rtd->acp_mmio,  in acp_get_byte_count()
1025 	byte_count.bcount.low  = acp_reg_read(rtd->acp_mmio,  in acp_get_byte_count()
1054 			dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr);  in acp_dma_pointer()
1102 	config_acp_dma_channel(rtd->acp_mmio,  in acp_dma_prepare()
1106 	config_acp_dma_channel(rtd->acp_mmio,  in acp_dma_prepare()
1130 				acp_dma_cap_channel_disable(rtd->acp_mmio,  in acp_dma_trigger()
1132 				acp_dma_cap_channel_enable(rtd->acp_mmio,  in acp_dma_trigger()
1136 				acp_dma_cap_channel_disable(rtd->acp_mmio,  in acp_dma_trigger()
1138 				acp_dma_cap_channel_enable(rtd->acp_mmio,  in acp_dma_trigger()
1141 			acp_dma_start(rtd->acp_mmio, rtd->ch1, true);  in acp_dma_trigger()
1143 			acp_dma_start(rtd->acp_mmio, rtd->ch1, true);  in acp_dma_trigger()
1144 			acp_dma_start(rtd->acp_mmio, rtd->ch2, true);  in acp_dma_trigger()
1151 		acp_dma_stop(rtd->acp_mmio, rtd->ch2);  in acp_dma_trigger()
1152 		ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);  in acp_dma_trigger()
1213 					acp_set_sram_bank_state(adata->acp_mmio,  in acp_dma_close()
1228 					acp_set_sram_bank_state(adata->acp_mmio,  in acp_dma_close()
1241 		acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);  in acp_dma_close()
1274 	audio_drv_data->acp_mmio = devm_platform_ioremap_resource(pdev, 0);  in acp_audio_probe()
1275 	if (IS_ERR(audio_drv_data->acp_mmio))  in acp_audio_probe()
1276 		return PTR_ERR(audio_drv_data->acp_mmio);  in acp_audio_probe()
1306 	status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type);  in acp_audio_probe()
1331 	status = acp_deinit(adata->acp_mmio);  in acp_audio_remove()
1344 	status = acp_init(adata->acp_mmio, adata->asic_type);  in acp_pcm_resume()
1358 				acp_set_sram_bank_state(adata->acp_mmio, bank,  in acp_pcm_resume()
1362 		config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);  in acp_pcm_resume()
1368 				acp_set_sram_bank_state(adata->acp_mmio, bank,  in acp_pcm_resume()
1372 		config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);  in acp_pcm_resume()
1378 			config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);  in acp_pcm_resume()
1383 			config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);  in acp_pcm_resume()
1388 			config_acp_dma(adata->acp_mmio, rtd, adata->asic_type);  in acp_pcm_resume()
1391 	acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);  in acp_pcm_resume()
1400 	status = acp_deinit(adata->acp_mmio);  in acp_pcm_runtime_suspend()
1403 	acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);  in acp_pcm_runtime_suspend()
1412 	status = acp_init(adata->acp_mmio, adata->asic_type);  in acp_pcm_runtime_resume()
1417 	acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB);  in acp_pcm_runtime_resume()