Lines Matching full:cdsp
152 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); in vx2_reset_dsp()
158 vx_outl(chip, CDSP, chip->regCDSP); in vx2_reset_dsp()
172 /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */ in vx2_test_xilinx()
173 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK); in vx2_test_xilinx()
181 /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */ in vx2_test_xilinx()
182 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK); in vx2_test_xilinx()
192 /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */ in vx2_test_xilinx()
193 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK); in vx2_test_xilinx()
201 /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */ in vx2_test_xilinx()
202 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK); in vx2_test_xilinx()
473 /* Set the interrupt enable bit to 1 in CDSP register */ in vx2_validate_irq()
483 vx_outl(chip, CDSP, chip->regCDSP); in vx2_validate_irq()
725 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); in vx2_reset_codec()
726 vx_inl(chip, CDSP); in vx2_reset_codec()
730 vx_outl(chip, CDSP, chip->regCDSP); in vx2_reset_codec()
731 vx_inl(chip, CDSP); in vx2_reset_codec()