Lines Matching refs:alc5505_coef_set
3950 static void alc5505_coef_set(struct hda_codec *codec, unsigned int index_reg, in alc5505_coef_set() function
3974 alc5505_coef_set(codec, 0x3000, 0x000c); /* DSP CPU stop */ in alc5505_dsp_halt()
3975 alc5505_coef_set(codec, 0x880c, 0x0008); /* DDR enter self refresh */ in alc5505_dsp_halt()
3976 alc5505_coef_set(codec, 0x61c0, 0x11110080); /* Clock control for PLL and CPU */ in alc5505_dsp_halt()
3977 alc5505_coef_set(codec, 0x6230, 0xfc0d4011); /* Disable Input OP */ in alc5505_dsp_halt()
3978 alc5505_coef_set(codec, 0x61b4, 0x040a2b03); /* Stop PLL2 */ in alc5505_dsp_halt()
3979 alc5505_coef_set(codec, 0x61b0, 0x00005b17); /* Stop PLL1 */ in alc5505_dsp_halt()
3980 alc5505_coef_set(codec, 0x61b8, 0x04133303); /* Stop PLL3 */ in alc5505_dsp_halt()
3982 alc5505_coef_set(codec, 0x6220, (val | 0x3000)); /* switch Ringbuffer clock to DBUS clock */ in alc5505_dsp_halt()
3987 alc5505_coef_set(codec, 0x61b8, 0x04133302); in alc5505_dsp_back_from_halt()
3988 alc5505_coef_set(codec, 0x61b0, 0x00005b16); in alc5505_dsp_back_from_halt()
3989 alc5505_coef_set(codec, 0x61b4, 0x040a2b02); in alc5505_dsp_back_from_halt()
3990 alc5505_coef_set(codec, 0x6230, 0xf80d4011); in alc5505_dsp_back_from_halt()
3991 alc5505_coef_set(codec, 0x6220, 0x2002010f); in alc5505_dsp_back_from_halt()
3992 alc5505_coef_set(codec, 0x880c, 0x00000004); in alc5505_dsp_back_from_halt()
4001 alc5505_coef_set(codec, 0x61b0, 0x5b14); /* PLL1 control */ in alc5505_dsp_init()
4002 alc5505_coef_set(codec, 0x61b0, 0x5b16); in alc5505_dsp_init()
4003 alc5505_coef_set(codec, 0x61b4, 0x04132b00); /* PLL2 control */ in alc5505_dsp_init()
4004 alc5505_coef_set(codec, 0x61b4, 0x04132b02); in alc5505_dsp_init()
4005 alc5505_coef_set(codec, 0x61b8, 0x041f3300); /* PLL3 control*/ in alc5505_dsp_init()
4006 alc5505_coef_set(codec, 0x61b8, 0x041f3302); in alc5505_dsp_init()
4008 alc5505_coef_set(codec, 0x61b8, 0x041b3302); in alc5505_dsp_init()
4009 alc5505_coef_set(codec, 0x61b8, 0x04173302); in alc5505_dsp_init()
4010 alc5505_coef_set(codec, 0x61b8, 0x04163302); in alc5505_dsp_init()
4011 alc5505_coef_set(codec, 0x8800, 0x348b328b); /* DRAM control */ in alc5505_dsp_init()
4012 alc5505_coef_set(codec, 0x8808, 0x00020022); /* DRAM control */ in alc5505_dsp_init()
4013 alc5505_coef_set(codec, 0x8818, 0x00000400); /* DRAM control */ in alc5505_dsp_init()
4017 alc5505_coef_set(codec, 0x6220, 0x2002010f); /* I/O PAD Configuration */ in alc5505_dsp_init()
4019 alc5505_coef_set(codec, 0x6220, 0x6002018f); in alc5505_dsp_init()
4021 alc5505_coef_set(codec, 0x61ac, 0x055525f0); /**/ in alc5505_dsp_init()
4022 alc5505_coef_set(codec, 0x61c0, 0x12230080); /* Clock control */ in alc5505_dsp_init()
4023 alc5505_coef_set(codec, 0x61b4, 0x040e2b02); /* PLL2 control */ in alc5505_dsp_init()
4024 alc5505_coef_set(codec, 0x61bc, 0x010234f8); /* OSC Control */ in alc5505_dsp_init()
4025 alc5505_coef_set(codec, 0x880c, 0x00000004); /* DRAM Function control */ in alc5505_dsp_init()
4026 alc5505_coef_set(codec, 0x880c, 0x00000003); in alc5505_dsp_init()
4027 alc5505_coef_set(codec, 0x880c, 0x00000010); in alc5505_dsp_init()