79 #define CM_REG_FUNCTRL1		0x04  macro
815 	val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);  in snd_cmipci_pcm_prepare()
823 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);  in snd_cmipci_pcm_prepare()
1240 			snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in setup_spdif_playback()
1256 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in setup_spdif_playback()
1326 		val = snd_cmipci_read(cm, CM_REG_FUNCTRL1);  in snd_cmipci_silence_hack()
1329 		snd_cmipci_write(cm, CM_REG_FUNCTRL1, val);  in snd_cmipci_silence_hack()
1385 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);  in snd_cmipci_capture_spdif_prepare()
1407 	snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_CAPTURE_SPDF);  in snd_cmipci_capture_spdif_hw_free()
2410 DEFINE_BIT_SWITCH_ARG(spdif_in, CM_REG_FUNCTRL1, CM_SPDF_1, 0, 0);
2411 DEFINE_BIT_SWITCH_ARG(spdif_out, CM_REG_FUNCTRL1, CM_SPDF_0, 0, 0);
2416 DEFINE_BIT_SWITCH_ARG(spdo2dac, CM_REG_FUNCTRL1, CM_SPDO2DAC, 0, 1);
2422 DEFINE_BIT_SWITCH_ARG(spdif_loop, CM_REG_FUNCTRL1, CM_SPDFLOOP, 0, 1);
2474 				snd_cmipci_set_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in snd_cmipci_spdout_enable_put()
2477 				snd_cmipci_clear_bit(chip, CM_REG_FUNCTRL1, CM_PLAYBACK_SPDF);  in snd_cmipci_spdout_enable_put()
2876 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_create_gameport()
2889 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_free_gameport()
2907 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);  in snd_cmipci_free()
3049 	snd_cmipci_write(cm, CM_REG_FUNCTRL1, 0);  in snd_cmipci_create()
3063 	snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_BREQ);  in snd_cmipci_create()
3135 			snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_UART_EN);  in snd_cmipci_create()
3140 				snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1,  in snd_cmipci_create()
3203 		snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_JYSTK_EN);  in snd_cmipci_create()
3268 	CM_REG_FUNCTRL1, CM_REG_CHFORMAT, CM_REG_LEGACY_CTRL, CM_REG_MISC_CTRL,