include/video/s1d13xxxfb.h

4  * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
34 #define S1DREG_LCD_CLK_CNF		0x0014	/* LCD Pixel Clock Configuration Register */
44 #define S1DREG_LCD_DISP_HWIDTH		0x0032	/* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/l…
45 #define S1DREG_LCD_NDISP_HPER		0x0034	/* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=N…
46 #define S1DREG_TFT_FPLINE_START		0x0035	/* TFT FPLINE Start Position Register */
47 #define S1DREG_TFT_FPLINE_PWIDTH	0x0036	/* TFT FPLINE Pulse Width Register. */
48 #define S1DREG_LCD_DISP_VHEIGHT0	0x0038	/* LCD Vertical Display Height Register 0 */
49 #define S1DREG_LCD_DISP_VHEIGHT1	0x0039	/* LCD Vertical Display Height Register 1 */
50 #define S1DREG_LCD_NDISP_VPER		0x003A	/* LCD Vertical Non-Display Period Register: (val)+1=NDlines …
51 #define S1DREG_TFT_FPFRAME_START	0x003B	/* TFT FPFRAME Start Position Register */
52 #define S1DREG_TFT_FPFRAME_PWIDTH	0x003C	/* TFT FPFRAME Pulse Width Register */
53 #define S1DREG_LCD_DISP_MODE		0x0040	/* LCD Display Mode Register */
54 #define S1DREG_LCD_MISC			0x0041	/* LCD Miscellaneous Register */
55 #define S1DREG_LCD_DISP_START0		0x0042	/* LCD Display Start Address Register 0 */
56 #define S1DREG_LCD_DISP_START1		0x0043	/* LCD Display Start Address Register 1 */
57 #define S1DREG_LCD_DISP_START2		0x0044	/* LCD Display Start Address Register 2 */
58 #define S1DREG_LCD_MEM_OFF0		0x0046	/* LCD Memory Address Offset Register 0 */
59 #define S1DREG_LCD_MEM_OFF1		0x0047	/* LCD Memory Address Offset Register 1 */
60 #define S1DREG_LCD_PIX_PAN		0x0048	/* LCD Pixel Panning Register */
61 #define S1DREG_LCD_DISP_FIFO_HTC	0x004A	/* LCD Display FIFO High Threshold Control Register */
62 #define S1DREG_LCD_DISP_FIFO_LTC	0x004B	/* LCD Display FIFO Low Threshold Control Register */
64 #define S1DREG_CRT_NDISP_HPER		0x0052	/* CRT/TV Horizontal Non-Display Period Register */
69 #define S1DREG_CRT_NDISP_VPER		0x0058	/* CRT/TV Vertical Non-Display Period Register */
82 #define S1DREG_LCD_CUR_CTL		0x0070	/* LCD Ink/Cursor Control Register */
83 #define S1DREG_LCD_CUR_START		0x0071	/* LCD Ink/Cursor Start Address Register */
84 #define S1DREG_LCD_CUR_XPOS0		0x0072	/* LCD Cursor X Position Register 0 */
85 #define S1DREG_LCD_CUR_XPOS1		0x0073	/* LCD Cursor X Position Register 1 */
86 #define S1DREG_LCD_CUR_YPOS0		0x0074	/* LCD Cursor Y Position Register 0 */
87 #define S1DREG_LCD_CUR_YPOS1		0x0075	/* LCD Cursor Y Position Register 1 */
88 #define S1DREG_LCD_CUR_BCTL0		0x0076	/* LCD Ink/Cursor Blue Color 0 Register */
89 #define S1DREG_LCD_CUR_GCTL0		0x0077	/* LCD Ink/Cursor Green Color 0 Register */
90 #define S1DREG_LCD_CUR_RCTL0		0x0078	/* LCD Ink/Cursor Red Color 0 Register */
91 #define S1DREG_LCD_CUR_BCTL1		0x007A	/* LCD Ink/Cursor Blue Color 1 Register */
92 #define S1DREG_LCD_CUR_GCTL1		0x007B	/* LCD Ink/Cursor Green Color 1 Register */
93 #define S1DREG_LCD_CUR_RCTL1		0x007C	/* LCD Ink/Cursor Red Color 1 Register */
94 #define S1DREG_LCD_CUR_FIFO_HTC		0x007E	/* LCD Ink/Cursor FIFO High Threshold Register */
128 #define S1DREG_LKUP_MODE		0x01E0	/* Look-Up Table Mode Register */
129 #define S1DREG_LKUP_ADDR		0x01E2	/* Look-Up Table Address Register */
130 #define S1DREG_LKUP_DATA		0x01E4	/* Look-Up Table Data Register */
133 #define S1DREG_CPU2MEM_WDOGT		0x01F4	/* CPU-to-Memory Access Watchdog Timer Register */